Abstract: A signal processing method, receiver and equalizing method are provided. The receiver comprises an estimator estimating a channel coefficient matrix from a received signal, a first calculation unit determining a channel correlation matrix based on the channel coefficient matrix a converter converting the channel correlation matrix into a circulant matrix. A second calculation unit determines equalization filter coefficients by applying a first transform to the real parts of a first subset of the terms in the first column of the circulant matrix and by applying a second transform to the imaginary parts of a second subset of the terms in the first column of the circulant matrix. An equalizer equalizes the received signal by using the determined equalization filter coefficients.

Abstract: A signal processing method, receiver and equalizing method are provided. The receiver comprises an estimator estimating a channel coefficient matrix from a received signal, a first calculation unit determining a channel correlation matrix based on the channel coefficient matrix a converter converting the channel correlation matrix into a circulant matrix. A second calculation unit determines equalization filter coefficients by applying a first transform to the real parts of a first subset of the terms in the first column of the circulant matrix and by applying a second transform to the imaginary parts of a second subset of the terms in the first column of the circulant matrix. An equalizer equalizes the received signal by using the determined equalization filter coefficients.

Abstract: A method and device for estimating a target chip index value in a code-division multiple access receiver. The receiver receives signals from a transmitter that uses a plurality of transmitted chips for data transmission through a plurality of multipath channels. As each channel is expressible as a channel impulse response at a given instant in time, the impulse response can be sampled and the samples indexed by a plurality of delay sample indices. The target chip index value can be determined based on the first moment of the delay sample indices over an impulse response.

Abstract: This invention describes a method of computing a fast Fourier transform (FFT) using enhanced processor computational capabilities for more efficient and flexible implementation of an electronic device (e.g., a linear equalizer) based on that FFT computing. A simple non-parallel instruction set processor (or just a non-parallel processor) containing complex multiplication and addition/subtraction capabilities is extended by adding additional registers and interconnects and a dedicated parallel instruction for calculating the FFT butterfly. The parallel instruction consists of orthogonal sub-instructions each controlling a section of the data path related to a corresponding section of the FFT butterfly.

Abstract: A method and device for estimating a target chip index value in a code-division multiple access receiver. The receiver receives signals from a transmitter that uses a plurality of transmitted chips for data transmission through a plurality of multipath channels. As each channel is expressible as a channel impulse response at a given instant in time, the impulse response can be sampled and the samples indexed by a plurality of delay sample indices. The target chip index value can be determined based on the first moment of the delay sample indices over an impulse response.