Abstract: A gas cell semiconductor chip assembly includes a gas cell including an alkali gas stored therein and a first semiconductor chip including a first resistive heating loop at a location corresponding to the gas cell to heat the gas cell and a second resistive heating loop around an outer perimeter of the first resistive heating loop. The second resistive heating loop is configured to cancel a magnetic field of the first resistive heating loop based on a current flowing through the first and second resistive heating loops.

Abstract: A gas cell semiconductor chip assembly includes a gas cell including an alkali gas stored therein and a first semiconductor chip including a first resistive heating loop at a location corresponding to the gas cell to heat the gas cell and a second resistive heating loop around an outer perimeter of the first resistive heating loop. The second resistive heating loop is configured to cancel a magnetic field of the first resistive heating loop based on a current flowing through the first and second resistive heating loops.

Abstract: An analog, single integrated circuit for providing centered video images. A light detector array which can be, e.g., a CCD or an array of phototransistors or silicon retinas, is scanned out to provide a video signal. Current summing lines along each row and column of the array are used as inputs to x and y position sensitive (computation) circuitry located on the edge of the pixel array. When the array utilizes silicon retinas, an absolute value circuit is added to restore low frequency information removed by the retinas to the current summing output. An on-chip sequencer uses the x and y position outputs to scan out the video image centered to the nearest pixel.

Abstract: A method and structure for minimizing one or more non-uniformities in image and position sensing detectors are provided. The structure is directed to a focal plane processor for removing non-uniformities which distort the computation of a desired property of an object of interest in an image field. The focal plane processor is capable of selectively disconnecting one or more rows and/or columns from further processing in the imaging array for those rows and/or columns which contribute to the presence of at least one non-uniformity in a video image generated by the focal plane processor. In one embodiment, the disconnection means is embodied as pre-processing circuitry which includes row and column shift registers which provide control signals to area-of-interest (AOI) switches. In another embodiment, the pixels which comprise the focal plane array are constructed in a manner which facilitates their individual isolation.

Abstract: A metal oxide semiconductor field effect transistor (“MOSFET”) layout with small width-length ratio allows for greater flexibility in design and density in dimension than the conventional annular technique is provided. Accordingly, higher density MOSFET of this layout gives more devices on a single semiconductor wafer. An additional benefit of this layout is a reduced current density at the enclosed terminal wherein there is less localized heating and damages of materials composing the transistor.

Abstract: A method and structure for minimizing one or more non-uniformities in image and position sensing detectors are provided. The structure is directed to a focal plane processor for removing non-uniformities which distort the computation of a de-sired property of an object of interest in an image field. The focal plane processor is capable of selectively disconnecting one or more rows and/or columns from further processing in the imaging array for those rows and/or columns which contribute to the presence of at least one non-uniformity in a video image generated by the focal plane processor. In one embodiment, the disconnection means is embodied as pre-processing circuitry which includes row and column shift registers which provide control signals to area-of-interest (AOI) switches. In another embodiment, the pixels which comprise the focal plane array are constructed in a manner which facilitates their individual isolation.

Abstract: An autonomous navigation system for an orbital platform incorporating a global positioning system based navigation device optimized for low-Earth orbit and medium-Earth orbit applications including a 12-channel, GPS tracking application-specific integrated circuit operating in concert with a microprocessor implementing an extended Kalman filter and orbit propagator which autonomously generates estimates of position, velocity, and time to enable planing, prediction and execution of event-based commanding of mission operations.

Abstract: An autonomous navigation system for an orbital platform incorporating a global positioning system based navigation device optimized for low-Earth orbit and medium-Earth orbit applications including a 12 channel, GPS tracking application-specific integrated circuit (15) operating in concert with a computer system (90) implementing an extended Kalman filter and orbit propagator which autonomously generates estimates of position, velocity and time to enable planning, prediction and execution of event-based commanding of mission operations.

Abstract: An analog, single integrated circuit for providing centered video images. A light detector array which can be, e.g., a CCD or an array of phototransistors or silicon retinas, is scanned out to provide a video signal. Current summing lines along each row and column of the array are used as inputs to x and y position sensitive (computation) circuitry located on the edge of the pixel array. When the array utilizes silicon retinas, an absolute value circuit is added to restore low frequency information removed by the retinas to the current summing output. An on-chip sequencer uses the x and y position outputs to scan out the video image centered to the nearest pixel.

Abstract: A cellular logic operation processor for performing transformations, according to a controlled sequence, of the data points of a first matrix into a corresponding number of data points of a second matrix. The processor includes a plurality of operably connected digital storage devices for temporarily and sequentially storing each neighborhood of data points from a first matrix, wherein a neighborhood of data points is comprised of a central data point and its surrounding data points in a matrix. The processor also includes a plurality of taps wherein each tap is electrically connected to a digital storage device such that the tap electrically indicates the state of the data point stored in the digital storage device. A look-up table is also provided having stored therein a plurality of transformation values which are individually addressable in accordance with the combined states indicated by the taps.