Patents by Inventor Kimberly A. Malone

Kimberly A. Malone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220365709
    Abstract: Systems, apparatuses and methods may provide for technology that identifies a first namespace descriptor, a device memory descriptor, and a first request to execute a program on a logical volume that spans a plurality of physical drives, selects a first target drive from the plurality of physical drives based on the first namespace descriptor, and configures the first target drive to execute the program on first input data associated with the first namespace descriptor and write a first output of the program to a first memory region in an internal memory of the first target drive. In one example, the technology maps the device memory descriptor to the first memory region.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 17, 2022
    Inventors: Arun Raghunath, Scott Peterson, Kimberly A. Malone
  • Patent number: 11036642
    Abstract: A semiconductor chip is described. The semiconductor chip includes memory address decoder logic circuitry comprising different memory address bit manipulation paths to respectively impose different memory interleaving schemes for memory accesses directed to artificial intelligence information in a memory and non artificial intelligence information in the memory. The artificial intelligence information is to be processed with artificial intelligence logic circuitry disposed locally to the memory.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Dimitrios Ziakas, Mark A. Schmisseur, Kshitij A. Doshi, Kimberly A. Malone
  • Publication number: 20190251034
    Abstract: A semiconductor chip is described. The semiconductor chip includes memory address decoder logic circuitry comprising different memory address bit manipulation paths to respectively impose different memory interleaving schemes for memory accesses directed to artificial intelligence information in a memory and non artificial intelligence information in the memory. The artificial intelligence information is to be processed with artificial intelligence logic circuitry disposed locally to the memory.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 15, 2019
    Inventors: Francesc GUIM BERNAT, Dimitrios ZIAKAS, Mark A. SCHMISSEUR, Kshitij A. DOSHI, Kimberly A. MALONE
  • Patent number: 10360120
    Abstract: A high availability (HA) failover manager maintains data availability of one or more input/output (I/O) resources in a cluster by ensuring that each I/O resource is available (e.g., mounted) on a hosting node of the cluster and that each I/O resource may be available on one or more partner nodes of the cluster if a node (i.e., a local node) were to fail. The HA failover manager (HA manager) processes inputs from various sources of the cluster to determine whether failover is enabled for a local node and each partner node in an HA group, and for triggering failover of the I/O resources to the partner node as necessary. For each I/O resource, the HA manager may track state information including (i) a state of the I/O resource (e.g., mounted or un-mounted); (ii) the partner node(s) ability to service the I/O resource; and (iii) whether a non-volatile log recording I/O requests is synchronized to the partner node(s).
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: July 23, 2019
    Assignee: NetApp, Inc.
    Inventors: Steven S. Watanabe, Stephen H. Strange, John Muth, Kimberly A. Malone, Kayuri H. Patel
  • Patent number: 10206442
    Abstract: The turn signal riding gloves is a pair of gloves with lights integrated into an exterior surface that form turn signals or a braking signal light. Each of the pair of gloves operates independent of one another. Each of the pair of gloves includes a powering member that is wired in between a plurality of buttons and the plurality of lights. The plurality of buttons may be linearly aligned along a side surface of an index finger of the respective glove. In use, the motorcyclist simply raises an applicable hand and corresponding glove into the air, and pressing one of the plurality of buttons in order to generate a brake light signal, left turn signal, or right turn signal.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: February 19, 2019
    Inventors: Kimberly Malone-Jones, Rufus Jones
  • Publication number: 20190042365
    Abstract: Examples include techniques for performing read-optimized lazy erasure encoding of data streams. An embodiment includes receiving a request to write a stream of data, separating the stream into a first plurality of extents, storing a primary replica and one or more additional replicas of each extent of the separated stream to a plurality of data storage nodes, and updating a list of extents to be erasure encoded. The embodiment further includes when an erasure encoded stripe can be created, getting the data for each of the extents of the erasure encoded stripe, calculating parity extents for unencoded extents of the erasure encoded stripe, writing the parity extents to a second plurality of data storage nodes, and deleting the one or more additional replicas of the extents of the erasure encoded stripe from the first plurality of data storage nodes.
    Type: Application
    Filed: September 26, 2018
    Publication date: February 7, 2019
    Inventors: Kimberly A. MALONE, Steven C. MILLER
  • Publication number: 20170351589
    Abstract: A high availability (HA) failover manager maintains data availability of one or more input/output (I/O) resources in a cluster by ensuring that each I/O resource is available (e.g., mounted) on a hosting node of the cluster and that each I/O resource may be available on one or more partner nodes of the cluster if a node (i.e., a local node) were to fail. The HA failover manager (HA manager) processes inputs from various sources of the cluster to determine whether failover is enabled for a local node and each partner node in an HA group, and for triggering failover of the I/O resources to the partner node as necessary. For each I/O resource, the HA manager may track state information including (i) a state of the I/O resource (e.g., mounted or un-mounted); (ii) the partner node(s) ability to service the I/O resource; and (iii) whether a non-volatile log recording I/O requests is synchronized to the partner node(s).
    Type: Application
    Filed: August 25, 2017
    Publication date: December 7, 2017
    Inventors: Steven S. Watanabe, Stephen H. Strange, John Muth, Kimberly A. Malone, Kayuri H. Patel
  • Patent number: 9785525
    Abstract: A high availability (HA) failover manager maintains data availability of one or more input/output (I/O) resources in a cluster by ensuring that each I/O resource is available (e.g., mounted) on a hosting node of the cluster and that each I/O resource may be available on one or more partner nodes of the cluster if a node (i.e., a local node) were to fail. The HA failover manager (HA manager) processes inputs from various sources of the cluster to determine whether failover is enabled for a local node and each partner node in an HA group, and for triggering failover of the I/O resources to the partner node as necessary. For each I/O resource, the HA manager may track state information including (i) a state of the I/O resource (e.g., mounted or un-mounted); (ii) the partner node(s) ability to service the I/O resource; and (iii) whether a non-volatile log recording I/O requests is synchronized to the partner node(s).
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: October 10, 2017
    Assignee: NetApp, Inc.
    Inventors: Steven S. Watanabe, Stephen H. Strange, John Muth, Kimberly A. Malone, Kayuri H. Patel
  • Publication number: 20170091056
    Abstract: A high availability (HA) failover manager maintains data availability of one or more input/output (I/O) resources in a cluster by ensuring that each I/O resource is available (e.g., mounted) on a hosting node of the cluster and that each I/O resource may be available on one or more partner nodes of the cluster if a node (i.e., a local node) were to fail. The HA failover manager (HA manager) processes inputs from various sources of the cluster to determine whether failover is enabled for a local node and each partner node in an HA group, and for triggering failover of the I/O resources to the partner node as necessary. For each I/O resource, the HA manager may track state information including (i) a state of the I/O resource (e.g., mounted or un-mounted); (ii) the partner node(s) ability to service the I/O resource; and (iii) whether a non-volatile log recording I/O requests is synchronized to the partner node(s).
    Type: Application
    Filed: September 24, 2015
    Publication date: March 30, 2017
    Inventors: Steven S. Watanabe, Stephen H. Strange, John Muth, Kimberly A. Malone, Kayuri H. Patel