Abstract: A computer system is provided, comprising system memory and a memory controller which resides on a system bus for controlling access to the system memory, a bus interface unit and a direct memory access controller also residing on the system bus, and a central processing unit electrically connected with the memory controller which is able to read and write data to the system memory via the memory controller. The memory controller and the bus interface unit each operate, when either is in control of the system bus, at a clock frequency which is a multiple of the clock frequency at which the direct memory access controller operates on the system bus. The memory controller and the bus interface unit each operate, when the direct memory access controller is in control of the system bus, at the same clock frequency as that of the direct memory access controller. The clock frequencies of the memory controller, the bus interface unit and the direct memory access controller are each synchronized in time.

Abstract: A computer system that has a main memory and a writeback cache memory also has an I/O device capable of data streaming. A memory controller responds to signals that the I/O device will perform a burst transfer of data to the main memory and blocks potential writebacks from the cache memory to the I/O device. Potential writing over of the data from the I/O device by a flushed cache line written back to the main memory is thereby prevented. The system performance is increased since the data from the I/O device can be written to the main memory without waiting for a snoop cycle and a writeback to be performed.