Patents by Inventor Kimberly L. Pierce

Kimberly L. Pierce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145383
    Abstract: An integrated circuit structure includes a device layer including a first set of devices and a second set of devices. An interconnect layer is above the device layer, where the interconnect layer includes one or more conductive interconnect features within dielectric material. In an example, a first ring structure including conductive material extends within the interconnect layer, and a second ring structure including conductive material extends within the interconnect layer. In an example, the second ring structure is non-overlapping with the first ring structure. In an example, the first ring structure is above the first set of devices of the device layer, and the second ring structure is above the second set of devices of the device layer.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 2, 2024
    Applicant: Intel Corporation
    Inventors: June Choi, Keith E. Zawadzki, Kimberly L. Pierce, Mohammad Enamul Kabir
  • Patent number: 11950407
    Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Juan G. Alzate Vinasco, Travis W. Lajoie, Abhishek A. Sharma, Kimberly L Pierce, Elliot N. Tan, Yu-Jin Chen, Van H. Le, Pei-Hua Wang, Bernhard Sell
  • Publication number: 20230422463
    Abstract: SRAM devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to the edges of front or back faces of a support structure or a die on/in which the transistor resides, e.g., at an angle between about 10 and 80 degrees with respect to at least one of such edges. Implementing at least some of the transistors of SRAM cells as angled transistors may provide a promising way to increasing densities of SRAM cells on the limited real estate of semiconductor chips.
    Type: Application
    Filed: May 5, 2023
    Publication date: December 28, 2023
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Sagar Suthram, Kimberly L. Pierce, Elliot Tan, Pushkar Sharad Ranade, Shem Odhiambo Ogadhoh, Wilfred Gomes, Anand S. Murthy, Swaminathan Sivakumar, Tahir Ghani
  • Publication number: 20210305255
    Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventors: Juan G. ALZATE VINASCO, Travis W. LAJOIE, Abhishek A. SHARMA, Kimberly L. PIERCE, Elliot N. TAN, Yu-Jin CHEN, Van H. LE, Pei-Hua WANG, Bernhard SELL
  • Patent number: 7061237
    Abstract: An apparatus and method for remote NMR/MRI spectroscopy having an encoding coil with a sample chamber, a supply of signal carriers, preferably hyperpolarized xenon and a detector allowing the spatial and temporal separation of signal preparation and signal detection steps. This separation allows the physical conditions and methods of the encoding and detection steps to be optimized independently. The encoding of the carrier molecules may take place in a high or a low magnetic field and conventional NMR pulse sequences can be split between encoding and detection steps. In one embodiment, the detector is a high magnetic field NMR apparatus. In another embodiment, the detector is a superconducting quantum interference device. A further embodiment uses optical detection of Rb—Xe spin exchange. Another embodiment uses an optical magnetometer using non-linear Faraday rotation. Concentration of the signal carriers in the detector can greatly improve the signal to noise ratio.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: June 13, 2006
    Assignee: The Regents of the University of California
    Inventors: Alexander Pines, Sunil Saxena, Adam Moule, Megan Spence, Juliette A. Seeley, Kimberly L. Pierce, Song-I Han, Josef Granwehr
  • Publication number: 20030077224
    Abstract: An apparatus and method for remote NMR/MRI spectroscopy having an encoding coil with a sample chamber, a supply of signal carriers, preferably hyperpolarized xenon and a detector allowing the spatial and temporal separation of signal preparation and signal detection steps. This separation allows the physical conditions and methods of the encoding and detection steps to be optimized independently. The encoding of the carrier molecules may take place in a high or a low magnetic field and conventional NMR pulse sequences can be split between encoding and detection steps. In one embodiment, the detector is a high magnetic field NMR apparatus. In another embodiment, the detector is a superconducting quantum interference device. A further embodiment uses optical detection of Rb-Xe spin exchange. Another embodiment uses an optical magnetometer using non-linear Faraday rotation. Concentration of the signal carriers in the detector can greatly improve the signal to noise ratio.
    Type: Application
    Filed: October 9, 2002
    Publication date: April 24, 2003
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Alexander Pines, Sunil Saxena, Adam Moule, Megan Spence, Juliette A. Seeley, Kimberly L. Pierce, Song-I Han, Josef Granwehr