Patents by Inventor Kimiaki Ando
Kimiaki Ando has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040178366Abstract: In the case of drawing an oblique figure pattern, when drawing an oblique figure by using a slender rectangular beam, a problem occurs that edge roughness occurs at an oblique-side portion to deteriorate the drawing accuracy. The present invention solves the above problem and provides an electron-beam drawing apparatus and an electron-beam drawing method capable of accurately drawing even an oblique figure.Type: ApplicationFiled: March 23, 2004Publication date: September 16, 2004Applicant: Hitachi, Ltd.Inventors: Kimiaki Ando, Haruo Yoda, Rikio Tomiyoshi, Masamichi Kawano
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Publication number: 20040008758Abstract: One code is generated by combining (including addition) 2 or more codes, correlation detection method which detects the correlation by multiplying such a generated code by the reception data. In communication system based on W-CDMA method, first spreading code (a·Cp) obtained by multiplying primary synchronization code with a predetermined coefficient and second spreading code (a·Cs) obtained by multiplying secondary synchronization code with a predetermined coefficient are added. Then, the third spreading code (a·Cp+a·Cs) obtained from such an addition is multiplied by the reception data, and correlation value is obtained after integrating the multiplication results. Thus, it is determined whether the reception data has been subjected to STTD diversity.Type: ApplicationFiled: January 16, 2003Publication date: January 15, 2004Inventor: Kimiaki Ando
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Publication number: 20030169060Abstract: A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined charged state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with the electron beam after a predetermined period of time from an instance when the electron beam is radiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.Type: ApplicationFiled: March 6, 2003Publication date: September 11, 2003Applicant: Hitachi, Ltd.Inventors: Hiroyuki Shinada, Mari Nozoe, Haruo Yoda, Kimiaki Ando, Katsuhiro Kuroda, Yutaka Kaneko, Maki Tanaka, Shunji Maeda, Hitoshi Kubota, Aritoshi Sugimoto, Katsuya Sugiyama, Atsuko Takafuji, Yusuke Yajima, Hiroshi Tooyama, Tadao Ino, Takashi Hiroi, Kazushi Yoshimura, Yasutsugu Usami
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Patent number: 6559663Abstract: A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined charged state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with: the electron beam after a predetermined period of time from an instance when the electron beam is irradiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.Type: GrantFiled: October 25, 2001Date of Patent: May 6, 2003Assignee: Hitachi, Ltd.Inventors: Hiroyuki Shinada, Mari Nozoe, Haruo Yoda, Kimiaki Ando, Katsuhiro Kuroda, Yutaka Kaneko, Maki Tanaka, Shunji Maeda, Hitoshi Kubota, Aritoshi Sugimoto, Katsuya Sugiyama, Atsuko Takafuji, Yusuke Yajima, Hiroshi Tooyama, Tadao Ino, Takashi Hiroi, Kazushi Yoshimura, Yasutsugu Usami
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Patent number: 6525519Abstract: An amplitude detecting circuit (1) includes a simple digital filter (2) having a structure corresponding to a part where the energy is concentrated in the full impulse response of a signal processing digital filter (3). Concretely, for example, the amplitude detecting circuit (1) (simple digital filter (2)) includes only four central taps having coefficients of large absolute values and considerably affecting on the output amplitude among sixteen taps of the signal processing digital filter (3). By the amplitude detecting circuit (1), the amplitude of an output signal of the signal processing digital filter (3) can approximately be detected.Type: GrantFiled: June 28, 2001Date of Patent: February 25, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kimiaki Ando, Hiroki Shinde
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Patent number: 6403973Abstract: The present invention provides an electron beam exposure method and an exposure apparatus suitable for use in the electron beam exposure technology for performing exposure on a sample placed on a sample table by an electron beam while continuously moving the sample table, both of which are capable of performing high-accuracy and high-speed exposure without being affected by glitch noise of a DA converter used for trace deflection of the electron beam. Displacements of the position of the sample table and the position to apply the electron beam are determined and the determined displacements are divided into the amount of a shot synchronous trace and the amount of a real time trace each synchronized with shot timing for applying the electron beam to thereby reduce the amount of the real time trace, whereby degradation in exposure accuracy due to the glitch noise of the DA converter used for trace deflection is prevented from occurring. It is therefore possible to carry out high-accuracy exposure.Type: GrantFiled: February 7, 2000Date of Patent: June 11, 2002Assignee: Hitachi, Ltd.Inventors: Hiroyuki Takahashi, Masahide Okumura, Koji Nagata, Kimiaki Ando
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Patent number: 6373708Abstract: The pattern line width of a coil is partially widened in a predetermined dimension and wiring patterns of a coil on the surface side and a coil on the rear side are arranged so as not to be in overlapped positions. Consequently, a direct current resistance of the coil can be reduced and an adverse influence by a self resonance of the coil on a communication can be reduced.Type: GrantFiled: August 13, 1999Date of Patent: April 16, 2002Assignees: Hitachi, Ltd., Hitachi Chemical Co., Ltd.Inventors: Kimiaki Ando, Takehiro Ohkawa, Kazuo Kaneko
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Publication number: 20020027440Abstract: A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined charged state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with the electron beam after a predetermined period of time from an instance when the electron beam is radiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.Type: ApplicationFiled: October 25, 2001Publication date: March 7, 2002Applicant: Hitachi, Ltd.Inventors: Hiroyuki Shinada, Mari Nozoe, Haruo Yoda, Kimiaki Ando, Katsuhiro Kuroda, Yutaka Kaneko, Maki Tanaka, Shunji Maeda, Hitoshi Kubota, Aritoshi Sugimoto, Katsuya Sugiyama, Atsuko Takafuji, Yusuke Yajima, Hiroshi Tooyama, Tadao Ino, Takashi Hiroi, Kazushi Yoshimura, Yasutsugu Usami
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Patent number: 6352202Abstract: A reader/writer (RW) requires identification information pieces of respective plural IC cards (A, B, C). The plural IC cards return the respective identification information pieces in response to the requirement by the reader/writer. Logical addresses are assigned to some IC cards among the plural IC cards respectively to cause the reader/writer to select them in response to the return of the identification information pieces by the plural IC cards. The IC cards selected by the reader/writer are controlled. The reader/writer cancels the assignment of the logical address to one of the selected IC cards. The logical address, the assignment of which has been canceled by the reader/writer, is assigned to an IC card among the plural IC cards to which any logical address has not been assigned yet. The IC card to which the logical address has just been assigned is controlled.Type: GrantFiled: January 12, 1999Date of Patent: March 5, 2002Assignee: Denso CorporationInventors: Masahiro Takiguchi, Kiyoshi Takahashi, Tatsuya Hirata, Shigeru Date, Hisanobu Dobashi, Shinji Nishimura, Kimiaki Ando, Tadashi Sato, Hiromi Sato, Toru Miura
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Publication number: 20020024020Abstract: In the case of drawing an oblique figure pattern, when drawing an oblique figure by using a slender rectangular beam, a problem occurs that edge roughness occurs at an oblique-side portion to deteriorate the drawing accuracy. The present invention solves the above problem and provides an electron-beam drawing apparatus and an electron-beam drawing method capable of accurately drawing even an oblique figure.Type: ApplicationFiled: August 22, 2001Publication date: February 28, 2002Inventors: Kimiaki Ando, Haruo Yoda, Rikio Tomiyoshi, Masamichi Kawano
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Publication number: 20020000842Abstract: An amplitude detecting circuit (1) comprises a simple digital filter (2) having a structure corresponding to a part where the energy is concentrated in the full impulse response of a signal processing digital filter (3). Concretely, for example, the amplitude detecting circuit (1) (simple digital filter (2)) comprises only four central taps having coefficients of large absolute values and considerably affecting on the output amplitude among sixteen taps of the signal processing digital filter (3). By the amplitude detecting circuit (1), the amplitude of an output signal of the signal processing digital filter (3) can approximately be detected.Type: ApplicationFiled: June 28, 2001Publication date: January 3, 2002Inventors: Kimiaki Ando, Hiroki Shinde
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Patent number: 6329826Abstract: A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined charged state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with the electron beam after a predetermined period of time from an instance when the electron beam is irradiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.Type: GrantFiled: March 14, 2000Date of Patent: December 11, 2001Assignee: Hitachi, Ltd.Inventors: Hiroyuki Shinada, Mari Nozoe, Haruo Yoda, Kimiaki Ando, Katsuhiro Kuroda, Yutaka Kaneko, Maki Tanaka, Shunji Maeda, Hitoshi Kubota, Aritoshi Sugimoto, Katsuya Sugiyama, Atsuko Takafuji, Yusuke Yajima, Hiroshi Tooyama, Tadao Ino, Takashi Hiroi, Kazushi Yoshimura, Yasutsugu Usami
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Publication number: 20010040185Abstract: A reader/writer (RW) requires identification information pieces of respective plural IC cards (A, B, C). The plural IC cards return the respective identification information pieces in response to the requirement by the reader/writer. Logical addresses are assigned to some IC cards among the plural IC cards respectively to cause the reader/writer to select them in response to the return of the identification information pieces by the plural IC cards. The IC cards selected by the reader/writer are controlled. The reader/writer cancels the assignment of the logical address to one of the selected IC cards. The logical address, the assignment of which has been canceled by the reader/writer, is assigned to an IC card among the plural IC cards to which any logical address has not been assigned yet. The IC card to which the logical address has just been assigned is controlled.Type: ApplicationFiled: January 12, 1999Publication date: November 15, 2001Inventors: MASAHIRO TAKIGUCHI, KIYOSHI TAKAHASHI, TATSUYA HIRATA, SHIGERU DATE, HISANOBU DOBASHI, SHINJU NISHIMURA, KIMIAKI ANDO, TADASHI SATO, HIROMI SATO, TORU MIURA
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Publication number: 20010033604Abstract: The pilot signal reception method of the present invention irregularly receives pilot symbols. That is, the pilot signal reception method performs irregular reception processing such as randomizing reception timings or changing reception timings according to reception situations as appropriate to reduce influences of fading. Randomization of reception timings is implemented by generating random timings using a random timing generation circuit.Type: ApplicationFiled: February 8, 2001Publication date: October 25, 2001Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kimiaki Ando, Hiroki Shinde
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Patent number: 6172363Abstract: A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined charged state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with the electron beam after a predetermined period of time from an instance when the electron beam is irradiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.Type: GrantFiled: March 4, 1997Date of Patent: January 9, 2001Assignee: Hitachi, Ltd.Inventors: Hiroyuki Shinada, Mari Nozoe, Haruo Yoda, Kimiaki Ando, Katsuhiro Kuroda, Yutaka Kaneko, Maki Tanaka, Shunji Maeda, Hitoshi Kubota, Aritoshi Sugimoto, Katsuya Sugiyama, Atsuko Takafuji, Yusuke Yajima, Hiroshi Tooyama, Tadao Ino, Takashi Hiroi, Kazushi Yoshimura, Yasutsugu Usami
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Patent number: 5999409Abstract: The pattern line width of a coil is partially widened in a predetermined dimension and wiring patterns of a coil on the surface side and a coil on the rear side are arranged so as not to be in overlapped positions. Consequently, a direct current resistance of the coil can be reduced and an adverse influence by a self resonance of the coil on a communication can be reduced.Type: GrantFiled: January 21, 1998Date of Patent: December 7, 1999Assignees: Hitachi, Ltd., Hitachi Chemical Co., Ltd.Inventors: Kimiaki Ando, Takehiro Ohkawa, Kazuo Kaneko
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Patent number: 5197097Abstract: A cell signal processing circuit is provided which is capable of precisely extracting a timing signal and a cell synchronizing signal. The cell signal processing circuit is principally composed of a signal adder circuit for adding a dummy signal comprising bit signals in a direct current balanced state to an end portion of respective inputted time series cell signals, and a separator circuit for separating and outputting the time series cell signals. Each dummy signal being composed of the same number of bits "0" and "1" is added to input signals in the form of time series cells such that signal cells are exchanged at a time of a bit "0" in the dummy signal.Type: GrantFiled: January 7, 1991Date of Patent: March 23, 1993Assignee: Hitachi, Ltd.Inventors: Yasushi Takahashi, Eiichi Amada, Kimiaki Ando, Masanori Miyata
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Patent number: 4943729Abstract: An electron beam lithography system having a contour resolving circuit for resolving original pattern data which is transferred from a host computer into contour portion pattern data and inner portion pattern data in accordance with the designated dimension, for adding flag data to enable the contour portion pattern data and the inner portion pattern data to be discriminated to the resolved pattern data, and for outputting the resolved pattern data with the flag data. By adding the flag data, the contour portion pattern data and inner portion pattern data can be easily discriminated. The operation to change the electron beam irradiation dose in accordance with the contour portion pattern and inner portion pattern can be fairly easily executed. A pattern can be drawn at a high accuracy while preventing a deformation of the drawn figure due to the proximity effect. A data processing amount in the computer can be reduced. A data transfer amount from the host computer can be also reduced.Type: GrantFiled: December 15, 1988Date of Patent: July 24, 1990Assignee: Hitachi, Ltd.Inventors: Kimiaki Ando, Mitsuo Ooyama, Norio Saitou
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Patent number: 4820928Abstract: A lithography apparatus in which a charged particle ray such as an electron beam or an ion beam is controlled to scan a desired region of a sample and thereby draw a pattern, including a framing pattern memory for storing therein closed framing lines of a pattern to be drawn in the form of dot images, a framing pattern generator for writing the framing lines of the pattern to be drawn into said framing pattern memory in the form of dot images, and a raster scanning circuit for scanning the framing pattern memory having stored therein closed framing lines of the pattern to be drawn and for generating a beam deflection address for drawing the pattern and a beam blanking control signal.Type: GrantFiled: October 9, 1987Date of Patent: April 11, 1989Assignee: Hitachi, Ltd.Inventors: Mitsuo Ooyama, Kimiaki Ando, Yoshio Kawamura, Norio Saitou, Takanori Simura, Hiroyuki Kohida
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Patent number: 4758973Abstract: A floating-point data processing apparatus operates to generate exponent data of fixed length from floating-point data composed of (a) a sign bit indicating a mantissa sign, (b) a first exponent part which has bit length determined in dependence upon a significant bit length necessary for binary expression of an exponent and which has all its bits determined at 1 or 0 in dependence upon the mantissa sign and the sign of said exponent, (c) a second exponent part which has its bit length determined in dependence upon the bit length of the first exponent part, which has a predetermined relationship determined in dependence upon the sign of the exponent and the mantissa sign with the significant bit part when the exponent is expressed in binary form, and the leading bit of which has a value different from the value of one bit of said first exponent part, and (d) a mantisa part which has a plurality of bits having a bit length determined in dependence upon the value of the exponent.Type: GrantFiled: September 5, 1985Date of Patent: July 19, 1988Assignee: Hitachi, Ltd.Inventors: Mitsuo Ooyama, Hozumi Hamada, Kimiaki Ando