Patents by Inventor Kimiaki Shimokawa

Kimiaki Shimokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7989324
    Abstract: The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon layer, and a stress relaxing film which cancels stress produced in the silicon nitride layer, wherein the silicon nitride layer and the stress relaxing film are provided on the back surface side.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: August 2, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kimiaki Shimokawa
  • Patent number: 7893522
    Abstract: The present invention includes a substrate structural body having a high electrostatic chuck force at a low voltage even when an insulated board is used, and a method for manufacturing the substrate structural body. As the substrate structural body, there is provided a substrate structural body for attaining its fixing by an electrostatic chuck mechanism, comprising at least a first polycrystalline silicon film formed on the back surface of a substrate comprised of an insulating material or its back and side surfaces, wherein a top layer of part of the back surface or the back and side surfaces is of a first silicon insulating film.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: February 22, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Shuichi Noda, Kimiaki Shimokawa
  • Publication number: 20090275189
    Abstract: The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon layer, and a stress relaxing film which cancels stress produced in the silicon nitride layer, wherein the silicon nitride layer and the stress relaxing film are provided on the back surface side.
    Type: Application
    Filed: July 8, 2009
    Publication date: November 5, 2009
    Inventor: Kimiaki Shimokawa
  • Patent number: 7564100
    Abstract: The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon layer, and a stress relaxing film which cancels stress produced in the silicon nitride layer, wherein the silicon nitride layer and the stress relaxing film are provided on the back surface side.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: July 21, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kimiaki Shimokawa
  • Publication number: 20090085174
    Abstract: The present invention includes a substrate structural body having a high electrostatic chuck force at a low voltage even when an insulated board is used, and a method for manufacturing the substrate structural body. As the substrate structural body, there is provided a substrate structural body for attaining its fixing by an electrostatic chuck mechanism, comprising at least a first polycrystalline silicon film formed on the back surface of a substrate comprised of an insulating material or its back and side surfaces, wherein a top layer of part of the back surface or the back and side surfaces is of a first silicon insulating film.
    Type: Application
    Filed: September 15, 2008
    Publication date: April 2, 2009
    Inventors: Shuichi Noda, Kimiaki Shimokawa
  • Publication number: 20060214230
    Abstract: The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon layer, and a stress relaxing film which cancels stress produced in the silicon nitride layer, wherein the silicon nitride layer and the stress relaxing film are provided on the back surface side.
    Type: Application
    Filed: March 17, 2006
    Publication date: September 28, 2006
    Inventor: Kimiaki Shimokawa
  • Patent number: 6682405
    Abstract: The polishing particle surface of the dresser of a chemical mechanical polishing apparatus used for a planarization process in manufacturing semiconductor devices is inclined. Moreover, the pressure to be applied onto the polishing surface of the dresser is linearly varied with a nonzero slope.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: January 27, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kimiaki Shimokawa
  • Publication number: 20020132562
    Abstract: The polish particle surface of the dresser of a chemical mechanical polish apparatus used for a planarization process in manufacturing semiconductor devices is inclined. Moreover, the pressure to be applied onto the polish surface of the dresser is linearly varied with a nonzero slope.
    Type: Application
    Filed: July 18, 2001
    Publication date: September 19, 2002
    Inventor: Kimiaki Shimokawa
  • Patent number: 5749772
    Abstract: A polishing pad is conditioned using a conditioning disc whose temperature is controlled upon Chemical Mechanical Polish. The temperature of the polishing pad remains unchanged upon conditioning and uniform CMP can be carried out.
    Type: Grant
    Filed: December 2, 1996
    Date of Patent: May 12, 1998
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kimiaki Shimokawa
  • Patent number: 5424253
    Abstract: A method for manufacturing an inter-layer insulating film (ex. O.sub.3, TEOS or NSG) with a superior surface flatness is disclosed to solve the problem that the surface of the inter-layer film formed on a certain under-layer substrate reveals roughness due to the influence of the substrate. It is provided a method for manufacturing O.sub.3 TEOS NSG film after doping nitrogen (N) atoms into the under-layer films, or after forming the under-layer films which contain nitrogen (N) atoms therein.
    Type: Grant
    Filed: March 4, 1993
    Date of Patent: June 13, 1995
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Takashi Usami, Masaki Yoshimaru, Kimiaki Shimokawa
  • Patent number: 4908333
    Abstract: An insulating film formed under a conductive film has a side wall defining a contact window and having the shape of a gently inclined curvilinear surface, so that the insulating film is able to provide a sufficient step coverage in the contact window. The insulating film is formed over the surface of a semiconductor substrate or a first conductive film. The insulating film has an increasing or decreasing refractive index over the depth thereof. A contact window is formed by selectively removing a portion of the insulating film using a photoresist pattern formed over the surface of the insulating film. A structure thus formed is subjected to an etching process capable of etching the upper layer of the insulating film at an etching rate higher than that for the lower layer of the same to etch the side wall of the insulating film defining the contact window into a gently inclined curvilinear surface, and then the photoresist pattern is removed.
    Type: Grant
    Filed: March 17, 1988
    Date of Patent: March 13, 1990
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kimiaki Shimokawa, Hiroshi Hoga