Abstract: On an epitaxial layer (4) serving as a collector layer are formed an emitter layer (10), an intrinsic base layer (9) surrounding the emitter layer (10) while permitting the surface of the emitter layer (10) to be exposed, external base layers (8) and link base layers (7) lying between the intrinsic base layer (9) and external base layers (8). The intrinsic base layer between the emitter layer and the epitaxial layer serving as the collector layer has a relatively high impurity concentration, so that a collector-emitter breakdown voltage is not decreased. The link base layers between the intrinsic base layer and external base layers has a relatively low impurity concentration to suppress decrease in emitter-base junction breakdown voltage.

Abstract: An n.sup.+ buried layer is formed on a surface of p.sup.- semiconductor substrate. An n.sup.- epitaxial growth layer and an n.sup.+ diffusion layer are formed on a surface of n.sup.+ buried layer. A p.sup.- base region and p.sup.+ external base region adjoining to each other are formed on a surface of n.sup.- epitaxial growth layer. An an n.sup.+ emitter region is formed at a surface of p.sup.- base region. An emitter electrode is formed adjacently to n.sup.+ emitter region. The emitter electrode is made of polycrystalline silicon doped with phosphorus at a concentration from 1.times.10.sup.20 cm.sup.-3 to 6.times.10.sup.20 cm.sup.-3.

Abstract: Insulator films (5) formed on an epitaxial layer (3) are opened such that external base regions (17) are not covered with the insulator films (5). Cross sections (14a) of the insulator films (5) are concavely sloped downward from the insulator films (5) toward an intrinsic base region (18) in the vicinity of the epitaxial layer (3). Base electrodes (15) which are in contact with the insulator films (5) along the cross sections (14a) are connected to the external base regions (17), so that coverage of the base electrodes (15) over the external base regions (17) is improved. The base resistance of a bipolar transistor (101) is reduced.

Abstract: An n.sup.- epitaxial layer 4 is formed on the top face of a p type semiconductor substrate 1. A p.sup.+ buried layer 20 is formed by implanting ions in the region extending over the p type semiconductor substrate 1 and the n.sup.- epitaxial layer 4. A p.sup.+ channel stop is formed in the upper layer of the p.sup.+ buried layer 20 by ion implantation. A p well is formed extending from the upper layer of the p.sup.+ channel stop to the top face of the n.sup.- epitaxial layer. An n channel MOS type field effect transistor 200 is formed in the p well 22. It is possible to reliably isolate an element from an adjacent element thereto because of the structure.

Abstract: There is disclosed a C-BiCMOS semiconductor device in which a base electrode (300) of an NPN bipolar transistor and a drain electrode (360) of a PMOS transistor are formed of the same polycrystalline semiconductor, in which a base electrode (310) of a PNP bipolar transistor and a drain electrode (350) of an NMOS transistor are formed of the same polycrystalline semiconductor, and in which a source electrode (530) of the PMOS transistor and a source electrode (520) of the NMOS transistor are formed of aluminium wiring. The C-BiCMOS semiconductor device achieves preferable electric conductivity in the source electrodes, size reduction in the drain electrodes, and simplified process steps in the formation of the base electrodes of the bipolar transistors, so that the size of the devices is reduced in simple process steps without deterioration of the electric conductivity.