Patents by Inventor Kimihide Saito

Kimihide Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7497908
    Abstract: Film coating unit has a substrate holder for holding a wafer, a coating solution discharge nozzle, and anti-drying boards opposed to a surface of the wafer. The coating solution is applied to the surface of the wafer in a direction from a front end toward a rear end of the wafer while relatively moving the substrate holder with respect to the coating solution discharge nozzle. During that time, the anti-drying boards are disposed at height of maximum 2 mm from the surface of the wafer so as to form dense atmosphere of a solvent between the surface of the wafer and the anti-drying board. Thereby the coating solution on or over the surface of the wafer is restrained from being dried and a coating film is formed with even thickness on or over the surface of the wafer.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: March 3, 2009
    Assignees: Sanyo Electric Co., Ltd, Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Mizuno, Yuuichi Mikata, Kimihide Saito
  • Publication number: 20070251449
    Abstract: The object of the present invention is to assuredly merge adjacent coating liquid lines when a coating liquid is applied on a surface of a substrate by a so-called scan coating. The coating is performed while the wafer W is oriented to an orientation such that the scanning direction of the coating nozzle liquid 5 crosses at the dicing lines D formed on the wafer W. After completion of the application, the wafer W is returned to the original orientation and thereafter the wafer W is unloaded from a coating film forming apparatus. The coating film forming apparatus stores a plurality of recipes defining coating conditions for each kind of wafer W. The coating conditions defined by the recipes include the orientation of the wafer W. The orientation of the wafer W is automatically set based on the selected recipe.
    Type: Application
    Filed: October 1, 2004
    Publication date: November 1, 2007
    Applicants: Tokyo Election Limited, Sanyo Electric Co., Ltd, Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Mizuno, Kimihide Saito, Yuuichi Mikata
  • Publication number: 20060199371
    Abstract: A semiconductor device includes a substrate and wirings located on the substrate. A passivation film including a first insulating film containing an impurity is located on the wirings. The first insulating film is formed from silicon oxide film materials containing greater than one percent carbon.
    Type: Application
    Filed: May 19, 2006
    Publication date: September 7, 2006
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Hideki Mizuhara, Yasunori Inoue, Hiroyuki Watanabe, Masaki Hirase, Kaori Misawa, Hiroyuki Aoe, Kimihide Saito, Hiroyasu Ishihara
  • Publication number: 20040265493
    Abstract: Film coating unit has a substrate holder for holding a wafer, a coating solution discharge nozzle, and anti-drying boards opposed to a surface of the wafer. The coating solution is applied to the surface of the wafer in a direction from a front end toward a rear end of the wafer while relatively moving the substrate holder with respect to the coating solution discharge nozzle. During that time, the anti-drying boards are disposed at height of maximum 2 mm from the surface of the wafer so as to form dense atmosphere of a solvent between the surface of the wafer and the anti-drying board. Thereby the coating solution on or over the surface of the wafer is restrained from being dried and a coating film is formed with even thickness on or over the surface of the wafer.
    Type: Application
    Filed: June 23, 2004
    Publication date: December 30, 2004
    Inventors: Tsuyoshi Mizuno, Yuuichi Mikata, Kimihide Saito
  • Patent number: 6437424
    Abstract: A barrier film of a SiON film is formed below an interlayer insulating film which is a single layer film or laminated film of an TEOS film or SOG film covering a floating gate 4 and control gate 6. The SiON film which is good in moisture blocking but poor in coverage is covered with another TEOS film which is better in coverage than the SiON film, thereby improving the barrier property of the barrier film. Such a configuration prevents moisture or H atoms contained in the TEOS film or SOG film from being diffused and trapped by the tunneling oxide film 3, thereby improving the trap-up rate and hence endurance characteristic and extending the operation life of a memory cell.
    Type: Grant
    Filed: February 16, 2000
    Date of Patent: August 20, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Noma, Masaji Hara, Kimihide Saito, Ryo Kawai, Yoichi Kanuma, Kazuo Okada
  • Publication number: 20010048147
    Abstract: A semiconductor device includes a substrate and wirings located on the substrate. A passivation film including a first insulating film containing an impurity is located on the wirings. The first insulating film is formed from silicon oxide film materials containing greater than one percent carbon.
    Type: Application
    Filed: March 9, 1998
    Publication date: December 6, 2001
    Inventors: HIDEKI MIZUHARA, YASUNORI INOUE, HIROYUKI WATANABE, MASAKI HIRASE, KAORI MISAWA, HIROYUKI AOE, KIMIHIDE SAITO, HIROYASU ISHIHARA
  • Patent number: 6071807
    Abstract: A semiconductor device including an interlayer insulation film is obtained, superior in planarization, insulation characteristics, and adhesion, suitable for microminiaturization of an element, and without inducing the problem of signal delay. In the fabrication method of this semiconductor device, an interconnection is formed on semiconductor substrate. Then, a first insulation film is formed so as to be in contact on the interconnection. Impurities are introduced into the first insulation film under a condition where the impurities arrive at least at the interconnection. As a result, the first insulation film is reduced in moisture and becomes less hygroscopic. Therefore, the insulation characteristics of the first insulation film is improved. When an SOG film superior in planarization is employed as the first insulation film, it is possible to directly form that SOG film on an underlying interconnection.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: June 6, 2000
    Assignee: Sanyo Electric Company, Ltd.
    Inventors: Hiroyuki Watanabe, Hideki Mizuhara, Kimihide Saito