Abstract: For detecting a failure of a logic circuit 11 provided in a semiconductor integrated circuit due to deterioration with age, or the like, there is provided a reference-producing circuit 12 using a logic different from the logic of the logic circuit 11. The reference-producing circuit 12 produces an abnormal/normal determination reference S for a predetermined output signal out output from the logic circuit 11. The reference-producing circuit 12 is made from only a portion of the logic of the logic circuit 11 or with a logic totally different from the logic of the logic circuit 11 to produce the determination reference S, so that the circuit scale of the reference-producing circuit 12 is smaller than that of the logic circuit 11. The determination reference S from the reference-producing circuit 12 and the output signal out from the logic circuit 11 are compared with each other by a determination circuit 13.

Abstract: For detecting a failure of a logic circuit 11 provided in a semiconductor integrated circuit due to deterioration with age, or the like, there is provided a reference-producing circuit 12 using a logic different from the logic of the logic circuit 11. The reference-producing circuit 12 produces an abnormal/normal determination reference S for a predetermined output signal out output from the logic circuit 11. The reference-producing circuit 12 is made from only a portion of the logic of the logic circuit 11 or with a logic totally different from the logic of the logic circuit 11 to produce the determination reference S, so that the circuit scale of the reference-producing circuit 12 is smaller than that of the logic circuit 11. The determination reference S from the reference-producing circuit 12 and the output signal out from the logic circuit 11 are compared with each other by a determination circuit 13.

Abstract: A semiconductor integrated circuits can send and receive signals to and form a configuration memory. The semiconductor integrated circuits is provided therein wiht an instruction memory, an instruction storage portion that stores reserved instructions as F instructions, and stores the substantially equivalent processing contents to the F instructions as substitute instructions for processing by the CPU, a pre-fetch portion, a history storage portion, a diagnosing portion for diagnosing the types of instructions, a reprogramming control portion for reprogramming the instructions, a CPU, an FPGA, a configuration data memory, a built-in memory, and a configuration data tag. When the configuration data of the F instruction does not exist in the FPGA, the substantially equivalent processing by FPGA is executed by the CPU by making use of the substitute instructions.

Abstract: A semiconductor integrated circuits can send and receive signals to and form a configuration memory. The semiconductor integrated circuits is provided therein wiht an instruction memory, an instruction storage portion that stores reserved instructions as F instructions, and stores the substantially equivalent processing contents to the F instructions as substitute instructions for processing by the CPU, a pre-fetch portion, a history storage portion, a diagnosing portion for diagnosing the types of instructions, a reprogramming control portion for reprogramming the instructions, a CPU, an FPGA, a configuration data memory, a built-in memory, and a configuration data tag. When the configuration data of the F instruction does not exist in the FPGA, the substantially equivalent processing by FPGA is executed by the CPU by making use of the substitute instructions.

Abstract: A semiconductor integrated circuits can send and receive signals to and form a configuration memory. The semiconductor integrated circuits is provided therein wiht an instruction memory, an instruction storage portion that stores reserved instructions as F instructions, and stores the substantially equivalent processing contents to the F instructions as substitute instructions for processing by the CPU, a pre-fetch portion, a history storage portion, a diagnosing portion for diagnosing the types of instructions, a reprogramming control portion for reprogramming the instructions, a CPU, an FPGA, a configuration data memory, a built-in memory, and a configuration data tag. When the configuration data of the F instruction does not exist in the FPGA, the substantially equivalent processing by FPGA is executed by the CPU by making use of the substitute instructions.