Patents by Inventor Kimihiko Deguchi

Kimihiko Deguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8507985
    Abstract: According to one embodiment, a semiconductor device, includes a semiconductor layer, a first base region of a first conductivity type, a first source region of a second conductivity type, a second base region of the first conductivity type, a back gate region of the first conductivity type, a drift region of the second conductivity type, a drain region of the second conductivity type, a first insulating region, a second insulating region, a gate oxide film, a first gate electrode, a second gate electrode, a first main electrode and a second main electrode. These constituent elements are provided on the surface of the semiconductor layer. The distance between the first base region and the first insulating region is not more than 1.8 ?m. The distance between the first base region and the first insulating region is shorter than a distance between the second base region and the second insulating region.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: August 13, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirofumi Hirasozu, Kimihiko Deguchi, Manji Obatake, Tomoko Matsudai
  • Publication number: 20110303979
    Abstract: According to one embodiment, a semiconductor device, includes a semiconductor layer, a first base region of a first conductivity type, a first source region of a second conductivity type, a second base region of the first conductivity type, a back gate region of the first conductivity type, a drift region of the second conductivity type, a drain region of the second conductivity type, a first insulating region, a second insulating region, a gate oxide film, a first gate electrode, a second gate electrode, a first main electrode and a second main electrode. These constituent elements are provided on the surface of the semiconductor layer. The distance between the first base region and the first insulating region is not more than 1.8 ?m. The distance between the first base region and the first insulating region is shorter than a distance between the second base region and the second insulating region.
    Type: Application
    Filed: March 18, 2011
    Publication date: December 15, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hirofumi HIRASOZU, Kimihiko Deguchi, Manji Obatake, Tomoko Matsudai
  • Patent number: 6153450
    Abstract: A semiconductor device according to the present invention is formed on a semiconductor chip and has a common module and a plurality of selectable modules. Each selectable module on the semiconductor chip performs a defined function and has a separate input power terminal. The device also has a voltage pad for connecting to a first voltage source having a first voltage level, so that the voltage pad supplies power to the input power terminal of each selectable module. The output of each selectable module may be connected to one common output pad, or alternatively, may be connected to a dedicated output pad. Also connected to each selectable module is a die/sort pad used for disconnecting a corresponding selectable module from the first voltage source. In the wiring between the first voltage source and the selectable modules, there is provided a plurality of fuses, each fuse having first and second terminals.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: November 28, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kimihiko Deguchi
  • Patent number: 5895942
    Abstract: A semiconductor device according to the present invention is formed on a semiconductor chip and has a common module and a plurality of selectable modules. Each selectable module on the semiconductor chip performs a defined function and has a separate input power terminal. The device also has a voltage pad for connecting to a first voltage source having a first voltage level, so that the voltage pad supplies power to the input power terminal of each selectable module. The output of each selectable module may be connected to one common output pad, or alternatively, may be connected to a dedicated output pad. Also connected to each selectable module is a die/sort pad used for disconnecting a corresponding selectable module from the first voltage source. In the wiring between the first voltage source and the selectable modules, there is provided a plurality of fuses, each fuse having first and second terminals.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: April 20, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kimihiko Deguchi