Abstract: A nonvolatile memory device includes: a semiconductor layer of a first conductivity type in which a first region, a second region, and a third region are partitioned by an isolation insulating layer; a semiconductor section of a second conductivity type provided in the first region and functioning as a control gate; a semiconductor section of the first conductivity type provided in the second region; a semiconductor section of the second conductivity type provided in the third region; an insulating layer provided on the semiconductor layer in the first to third regions; a floating gate electrode provided on the insulating layer across the first to third regions; impurity regions of the first conductivity type provided on each side of the floating gate electrode in the first region; impurity regions of the second conductivity type provided on each side of the floating gate electrode in the second region and functioning as either a source region or a drain region; and impurity regions of the first conductivity

Abstract: An integrated circuit device, a first direction being a direction extending from a first side which is a shorter side of the integrated circuit device to a third side opposed to the first side, a second direction being a direction extending from a second side which is a longer side of the integrated circuit device to a fourth side opposed to the second side, includes: a first to a Nth circuit blocks (N is an integer more than 2) arranged in the first direction. One of the first to the Nth circuit blocks is a programmable ROM block in which at least a part of data programmed is stored by a user; the programmable ROM block includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines; and the plurality of word lines extend in the second direction.

Abstract: A semiconductor device includes: a semiconductor layer having a shading target region; a semiconductor element provided on the semiconductor layer in the shading target region; a first interlayer dielectric provided on the semiconductor element; a plurality of first shading layers provided on the first interlayer dielectric; a second interlayer dielectric provided on at least the first shading layers; and a second shading layer provided on the second interlayer dielectric and having a predetermined pattern. The second shading layer has such a pattern that the second shading layer is positioned at least between the adjacent first shading layers.

Abstract: A nonvolatile memory device, including a plurality of memory cell blocks, N memory cell blocks (N is an integer equal to or greater than 2) being arranged in a row direction, L memory cell blocks (L is an integer equal to or greater than 2) being arranged in a column direction, and each of the memory cell blocks including M memory cells (M is an integer equal to or greater than 2), a plurality of wordlines, a plurality of first control gate lines, a plurality of first control gate switches, a plurality of second control gate lines, and a plurality of bitlines.

Abstract: A semiconductor device includes: a semiconductor layer having a shading target region; a semiconductor element provided on the semiconductor layer in the shading target region; a first interlayer dielectric provided on the semiconductor element; a plurality of first shading layers provided on the first interlayer dielectric; a second interlayer dielectric provided on at least the first shading layers; and a second shading layer provided on the second interlayer dielectric and having a predetermined pattern. The second shading layer has such a pattern that the second shading layer is positioned at least between the adjacent first shading layers.

Abstract: An integrated circuit device, a first direction being a direction extending from a first side which is a shorter side of the integrated circuit device to a third side opposed to the first side, a second direction being a direction extending from a second side which is a longer side of the integrated circuit device to a fourth side opposed to the second side, includes: a first to a Nth circuit blocks (N is an integer more than 2) arranged in the first direction. One of the first to the Nth circuit blocks is a programmable ROM block in which at least a part of data programmed is stored by a user; the programmable ROM block includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines; and the plurality of word lines extend in the second direction.

Abstract: A programmable ROM block provided in an integrated circuit device includes a memory cell having a single-layer-gate structure in which a floating gate used in common as gates of a write/read transistor and an erase transistor is opposite to a control gate formed of an impurity layer through an insulating layer. The memory cell the cell was backward has a triple-well structure including a shallow well of a first conductivity type formed on a deep well of a second conductivity type, a ring-shaped shallow well of the second conductivity type which encloses the shallow well of the first conductivity type, and top impurity regions formed in the shallow well of the first conductivity type and the ring-shaped shallow well of the second conductivity type.

Abstract: A nonvolatile semiconductor memory device having a small layout area includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction. The memory cell array includes source line diffusion layers, each of the source line diffusion layers extending along the row direction and connecting in common with the memory cells arranged in the row direction, bitline diffusion layers, element isolation regions which separate each of the bitline diffusion layers, and word gate common connection sections. Each of the memory cells includes a word gate and a select gate. One of the bitline diffusion layers is formed between two word gates adjacent in the column direction Y. Each of the word gate common connection sections is connected with the two word gates above one of the element isolation regions.

Abstract: A semiconductor device includes: a semiconductor layer having a shading target region; a semiconductor element provided on the semiconductor layer in the shading target region; a first interlayer dielectric provided on the semiconductor element; a plurality of first shading layers provided on the first interlayer dielectric; a second interlayer dielectric provided on at least the first shading layers; and a second shading layer provided on the second interlayer dielectric and having a predetermined pattern. The second shading layer has such a pattern that the second shading layer is positioned at least between the adjacent first shading layers.

Abstract: A nonvolatile memory device, wherein each of memory cells includes one of nonvolatile memory elements and one of wordline switches, wherein each of the wordlines connects in common gate electrodes of the wordline switches of memory cells arranged in the row direction; wherein each of the bitlines connects in common the wordline switches of memory cells arranged in the column direction; and wherein one of the first control gate lines connects in common control gate electrodes of the nonvolatile memory elements of M memory cells in one of memory cell blocks (M is an integer equal to or greater than 2); and wherein, when writing data into a desired memory cell, the wordline switches of the memory cells are turned ON by applying a wordline write voltage to a wordlines corresponding to the desired memory cell, a bitline write voltage is applied to the bitlines connected to the memory cells, and a control gate line write voltage is applied to one of the first control gate lines disposed in the memory cell block.

Abstract: A nonvolatile memory device includes: a semiconductor layer of a first conductivity type in which a first region, a second region, and a third region are partitioned by an isolation insulating layer; a semiconductor section of a second conductivity type provided in the first region and functioning as a control gate; a semiconductor section of the first conductivity type provided in the second region; a semiconductor section of the second conductivity type provided in the third region; an insulating layer provided on the semiconductor layer in the first to third regions; a floating gate electrode provided on the insulating layer across the first to third regions; impurity regions of the first conductivity type provided on each side of the floating gate electrode in the first region; impurity regions of the second conductivity type provided on each side of the floating gate electrode in the second region and functioning as either a source region or a drain region; and impurity regions of the first conductivity

Abstract: A nonvolatile semiconductor memory device having a small layout area includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction, wherein each of the memory cells includes a source region, a drain region, a channel region between the source region and the drain region, a word gate and a select gate disposed to face the channel region, and a nonvolatile memory element formed between the word gate and the channel region, wherein the wordline-and-selectline-driver-section includes a plurality of unit wordline-and-selectline-driver-sections, and wherein each of the unit wordline-and-selectline driver sections drives the select gates and the word gates of the memory cells in each row at a single potential.

Abstract: A nonvolatile semiconductor memory device having a small layout area includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction. The memory cell array includes source line diffusion layers, each of the source line diffusion layers extending along the row direction and connecting in common with the memory cells arranged in the row direction, bitline diffusion layers, element isolation regions which separate each of the bitline diffusion layers, and word gate common connection sections. Each of the memory cells includes a word gate and a select gate. One of the bitline diffusion layers is formed between two word gates adjacent in the column direction Y. Each of the word gate common connection sections is connected with the two word gates above one of the element isolation regions.

Abstract: A nonvolatile semiconductor memory device having a small layout area includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction, wherein each of the memory cells includes a source region, a drain region, a channel region between the source region and the drain region, a word gate and a select gate disposed to face the channel region, and a nonvolatile memory element formed between the word gate and the channel region, wherein the wordline-and-selectline-driver-section includes a plurality of unit wordline-and-selectline-driver-sections, and wherein each of the unit wordline-and-selectline driver sections drives the select gates and the word gates of the memory cells in each row at a single potential.