Patents by Inventor Kimihiro Yamanaka

Kimihiro Yamanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9110234
    Abstract: An optical module includes: a wiring substrate having an electrode pad on a main surface thereof; an optical waveguide disposed on the main surface of the wiring substrate; an optical semiconductor device mounted on a main surface of the optical waveguide, and having a connection pad disposed on a main surface on an optical waveguide side of the optical semiconductor device; and an electrically conductive member for providing electrical connection between the electrode pad and the connection pad. The optical waveguide has a hole passing therethrough in its thickness direction to leave the electrode pad exposed. The connection pad includes a projection which is at least partly inserted in the hole. The conductive member is disposed inside the hole, and makes connection with the projection and the electrode pad.
    Type: Grant
    Filed: December 26, 2011
    Date of Patent: August 18, 2015
    Assignee: KYOCERA Corporation
    Inventors: Kenji Terada, Kimihiro Yamanaka
  • Publication number: 20130272648
    Abstract: An optical module includes: a wiring substrate having an electrode pad on a main surface thereof; an optical waveguide disposed on the main surface of the wiring substrate; an optical semiconductor device mounted on a main surface of the optical waveguide, and having a connection pad disposed on a main surface on an optical waveguide side of the optical semiconductor device; and an electrically conductive member for providing electrical connection between the electrode pad and the connection pad. The optical waveguide has a hole passing therethrough in its thickness direction to leave the electrode pad exposed. The connection pad includes a projection which is at least partly inserted in the hole. The conductive member is disposed inside the hole, and makes connection with the projection and the electrode pad.
    Type: Application
    Filed: December 26, 2011
    Publication date: October 17, 2013
    Applicant: KYOCERA CORPORATION
    Inventors: Kenji Terada, Kimihiro Yamanaka
  • Patent number: 8446734
    Abstract: The invention relates to a circuit board having high density circuit and excellent connection reliability and lamination reliability. A resin fabric cloth (4) is provided by arranging single fibers (4a) or fiber bundles composed of a plurality of single fibers, which single fiber has a linear thermal expansion coefficient smaller than that of silicon, at least in two directions and alternately weaving them. In the board, the resin fabric cloth is covered with a resin portion (5) made of a resin material having a linear thermal expansion coefficient larger than that of silicon.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: May 21, 2013
    Assignee: Kyocera Corporation
    Inventors: Katsura Hayashi, Yutaka Tsukada, Kimihiro Yamanaka, Masaharu Shirai, Isamu Kirikihira
  • Patent number: 8350161
    Abstract: According to one of the invention, a circuit board comprises a conductive layer. The conductive layer includes a first land portion, a second land portion apart from the first land portion in a plan view, and a line portion connecting the first land portion and the second land portion to each other. The line portion includes lead portions through which a current is to flow and an opening portion arranged between the lead portions. The opening portion penetrates the conductive layer in a thickness direction.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: January 8, 2013
    Assignee: Kycera Corporation
    Inventors: Kimihiro Yamanaka, Manabu Ichinose, Satoshi Nakamura
  • Patent number: 8284557
    Abstract: Provided are a circuit board which meets requirement of suppressing peeling of a through hole conductor, a mounting structure and a method for manufacturing the circuit board. A circuit board (2) is provided with a base (5) and a through hole conductor (11). The base is provided with a fiber layer (9) and a through hole (S). The fiber layer has a single fiber (8) arranged along one direction and a resin for covering the single fiber (8). The through hole (S) penetrates the fiber layer (9), and the through hole conductor is formed in the through hole. The single fiber (8) partially protrudes to the side of the through hole conductor (11) from an inner wall surface of the through hole (S), and the protruded part is covered with the through hole conductor (11).
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: October 9, 2012
    Assignee: Kyocera Corporation
    Inventors: Yutaka Tsukada, Kimihiro Yamanaka, Kenji Terada
  • Patent number: 8253027
    Abstract: According to one embodiment of the invention, a circuit board comprises a conductive layer including a land portion and a line portion connected to the land portion, and; a conductor connected to a surface of the land portion. A planar shape of the connected portion between the conductor and the land portion has a elongated shape along a width direction of the line portion. A part of the connected portion is located within an imaginary region formed by imaginarily extending the line portion toward the land portion.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: August 28, 2012
    Assignee: Kyocera Corporation
    Inventors: Kimihiro Yamanaka, Manabu Ichinose, Satoshi Nakamura
  • Publication number: 20100259910
    Abstract: The invention relates to a circuit board having high density circuit and excellent connection reliability and lamination reliability. A resin fabric cloth (4) is provided by arranging single fibers (4a) or fiber bundles composed of a plurality of single fibers, which single fiber has a linear thermal expansion coefficient smaller than that of silicon, at least in two directions and alternately weaving them. In the board, the resin fabric cloth is covered with a resin portion (5) made of a resin material having a linear thermal expansion coefficient larger than that of silicon.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 14, 2010
    Applicant: KYOCERA CORPORATION
    Inventors: Katsura Hayashi, Yutaka Tsukada, Kimihiro Yamanaka, Masaharu Shirai, Isamu Kirikihira
  • Publication number: 20100254098
    Abstract: Provided are a circuit board which meets requirement of suppressing peeling of a through hole conductor, a mounting structure and a method for manufacturing the circuit board. A circuit board (2) is provided with a base (5) and a through hole conductor (11). The base is provided with a fiber layer (9) and a through hole (S). The fiber layer has a single fiber (8) arranged along one direction and a resin for covering the single fiber (8). The through hole (S) penetrates the fiber layer (9), and the through hole conductor is formed in the through hole. The single fiber (8) partially protrudes to the side of the through hole conductor (11) from an inner wall surface of the through hole (S), and the protruded part is covered with the through hole conductor (11).
    Type: Application
    Filed: October 17, 2008
    Publication date: October 7, 2010
    Applicant: KYOCERA CORPORATION
    Inventors: Yutaka Tsukada, Kimihiro Yamanaka, Kenji Terada
  • Publication number: 20100212947
    Abstract: According to one embodiment of the invention, a circuit board comprises a conductive layer including a land portion and a line portion connected to the land portion, and; a conductor connected to a surface of the land portion. A planar shape of the connected portion between the conductor and the land portion has a elongated shape along a width direction of the line portion. A part of the connected portion is located within an imaginary region formed by imaginarily extending the line portion toward the land portion.
    Type: Application
    Filed: February 24, 2010
    Publication date: August 26, 2010
    Applicant: KYOCERA CORPORATION
    Inventors: Kimihiro YAMANAKA, Manabu ICHINOSE, Satoshi NAKAMURA
  • Publication number: 20100193231
    Abstract: According to one of the invention, a circuit board comprises a conductive layer. The conductive layer includes a first land portion, a second land portion apart from the first land portion in a plan view, and a line portion connecting the first land portion and the second land portion to each other. The line portion includes lead portions through which a current is to flow and an opening portion arranged between the lead portions. The opening portion penetrates the conductive layer in a thickness direction.
    Type: Application
    Filed: January 29, 2010
    Publication date: August 5, 2010
    Applicant: KYOCERA CORPORATION
    Inventors: Kimihiro YAMANAKA, Manabu ICHINOSE, Satoshi NAKAMURA
  • Publication number: 20080164057
    Abstract: A printed wiring board has a via land, a glass epoxy resin layer, a via conductor, and a block layer. The via land is formed on a core layer. The glass epoxy resin layer is formed on the core layer and the via land. The via conductor is formed on the via land. The block layer is formed on the via land, between the via conductor and the glass epoxy resin layer.
    Type: Application
    Filed: July 5, 2004
    Publication date: July 10, 2008
    Inventors: Hiroyuki Mori, Kimihiro Yamanaka, Yasushi Kodama
  • Patent number: 7084355
    Abstract: A multilayer printed circuit board is provided in which microcracks or metallic migration is mitigated when a Resin Fill Plated Through Hole (RFP) is arranged near the edge thereof. The multilayer printed circuit board includes an inner layer having an RFP, outer layers, RFP lands, and conductor layers. The conductor layers are positioned over the RFP lands and the outer edges of the conductor layers extends outward further than the outer edges of the RFP lands. When the multilayer printed circuit board is heated, a stress is generated in and near the RFP. The conductor layers positioned so as to cover the RFP lands, exert a reaction against the stress to suppress generation of microcracks in the multilayer printed circuit board and thereby mitigate metallic migration in the board.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: Yoshiyuki Kosaka, Kazuyasu Sugisawa, Kimihiro Yamanaka
  • Patent number: 6985362
    Abstract: A printed circuit board on which a semiconductor chip is flip chip mounted, comprising a circuit pattern to which a conductive bump, provided in a corner portion of a semiconductor chip, is connected, an insulating layer for holding the circuit pattern, and a protection pad which is positioned on the insulating layer relative to the circuit pattern, to which the conductive bump is connected.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Mori, Yutaka Tsukada, Kimihiro Yamanaka
  • Publication number: 20040164060
    Abstract: A method and apparatus for drilling a hole through a printed circuit board is described using a laser beam such that the diameter of the top portion and the bottom portion of the hole are substantially equal. The laser beam is irradiated perpendicularly to a printed circuit board to drill a tapered hole having a top portion and a bottom portion wherein the diameter of the bottom portion is smaller than that of the top portion. Further, the laser beam 10 is irradiated to the tapered hole obliquely relative to the board 12 to equalize the diameters of the top and bottom portions to each other. By irradiating the laser beam 10 obliquely, a straight hole 14 can be formed.
    Type: Application
    Filed: February 20, 2004
    Publication date: August 26, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yoji Maeda, Yutaka Tsukada, Kimihiro Yamanaka, Masaharu Yasuda
  • Patent number: 6667559
    Abstract: A ball grid array module is provided. In particular, the ball grid array module includes a substrate with two layers of insulation positioned thereon. At least one cavity having a side wall and a bottom wall is positioned in the first and second layers of insulation. The ball grid array module is adapted for having a solder ball positioned on the bottom wall of the cavity. During heating and reflow of the solder ball, positioning of the solder ball in the cavity prevents dislodging of the solder ball.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: December 23, 2003
    Assignee: International Business Machines Corporation
    Inventors: Yutaka Tsukada, Kimihiro Yamanaka
  • Publication number: 20030214797
    Abstract: A multilayer printed circuit board is provided in which microcracks or metallic migration is mitigated when a Resin Fill Plated Through Hole (RFP) is arranged near the edge thereof. The multilayer printed circuit board includes an inner layer having an RFP, outer layers, RFP lands, and conductor layers. The conductor layers are positioned over the RFP lands and the outer edges of the conductor layers extends outward further than the outer edges of the RFP lands. When the multilayer printed circuit board is heated, a stress is generated in and near the RFP. The conductor layers positioned so as to cover the RFP lands, exert a reaction against the stress to suppress generation of microcracks in the multilayer printed circuit board and thereby mitigate metallic migration in the board.
    Type: Application
    Filed: April 8, 2003
    Publication date: November 20, 2003
    Applicant: International Business machines Corporation
    Inventors: Yoshiyuki Kosaka, Kazuyasu Sugisawa, Kimihiro Yamanaka
  • Publication number: 20020187585
    Abstract: A ball grid array module is provided. In particular, the ball grid array module includes a substrate with two layers of insulation positioned thereon. At least one cavity having a side wall and a bottom wall is positioned in the first and second layers of insulation. The ball grid array module is adapted for having a solder ball positioned on the bottom wall of the cavity. During heating and reflow of the solder ball, positioning of the solder ball in the cavity prevents dislodging of the solder ball.
    Type: Application
    Filed: June 4, 2002
    Publication date: December 12, 2002
    Applicant: International Business Machines Corporation
    Inventors: Yutaka Tsukada, Kimihiro Yamanaka
  • Patent number: 6486414
    Abstract: The present invention provides a through-hole structure for connecting a connector to a printed circuit board, the through-hole structure comprising a signal through-hole having a conductive layer therein for supplying a signal to the printed circuit board, power through-holes having a conductive layer therein for supplying power to the printed circuit board, and dielectric constant adjusting portions formed among the signal through-hole and the power through-holes. Moreover, the present invention provides a printed circuit board having the above-described through-hole structure formed therein.
    Type: Grant
    Filed: August 1, 2001
    Date of Patent: November 26, 2002
    Assignee: International Business Machines Corporation
    Inventors: Kaoru Kobayashi, Hiroyuki Mori, Kimihiro Yamanaka
  • Publication number: 20020027020
    Abstract: The present invention provides a through-hole structure for connecting a connector to a printed circuit board, the through-hole structure comprising a signal through-hole having a conductive layer therein for supplying a signal to the printed circuit board, power through-holes having a conductive layer therein for supplying power to the printed circuit board, and dielectric constant adjusting portions formed among the signal through-hole and the power through-holes. Moreover, the present invention provides a printed circuit board having the above-described through-hole structure formed therein.
    Type: Application
    Filed: August 1, 2001
    Publication date: March 7, 2002
    Applicant: International Business Machines Corporation
    Inventors: Kaoru Kobayashi, Hiroyuki Mori, Kimihiro Yamanaka
  • Publication number: 20020007964
    Abstract: A printed circuit board on which a semiconductor chip is flip chip mounted, comprising a circuit pattern to which a conductive bump, provided in a corner portion of a semiconductor chip, is connected, an insulating layer for holding the circuit pattern, and a protection pad which is positioned on the insulating layer relative to the circuit pattern, to which the conductive bump is connected.
    Type: Application
    Filed: September 5, 2001
    Publication date: January 24, 2002
    Applicant: International Business Machines Corporation
    Inventors: Hiroyuki Mori, Yutaka Tsukada, Kimihiro Yamanaka