Patents by Inventor Kimihito Kuwabara
Kimihito Kuwabara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8686544Abstract: It is possible to realize the following package structure. That is, a structure for applying a stress to a channel region is provided for a semiconductor chip itself. In a package manufacturing process, a low thermal expansion coefficient film is formed on a circuit face of an Si chip. Thus, distribution and magnitude of a desired stress can be secured for a channel region of a MOSFET in a mounted chip even after performance of the package manufacturing process. As a result, a mobility is increased and current driving power is enhanced.Type: GrantFiled: November 13, 2006Date of Patent: April 1, 2014Assignee: Panasonic CorporationInventors: Kenji Harafuji, Kimihito Kuwabara
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Patent number: 8330188Abstract: A semiconductor device 20 formed on a semiconductor chip substrate 30 has a plurality of circuit blocks made up of circuits each containing at least a metal oxide semiconductor (MOS) transistor 36, the circuit blocks being covered on top with a protective film 41 to protect the circuits. A plurality of bumps 23a, 23b, 23c are formed, at least via the protective film 41, only on circuit blocks whose current-carrying ability and threshold voltage do not satisfy predetermined values and which are in need of performance enhancement. The bumps 23a, 23b, 23c impose stresses on the MOS transistors 36, increasing the mobility of the MOS transistors 36 and thereby improving the performance of the semiconductor device 20.Type: GrantFiled: June 22, 2011Date of Patent: December 11, 2012Assignee: Panasonic CorporationInventors: Takayuki Yoshida, Kimihito Kuwabara, Takuma Motofuji, Toshiyuki Fukuda
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Publication number: 20110254094Abstract: A semiconductor device 20 formed on a semiconductor chip substrate 30 has a plurality of circuit blocks made up of circuits each containing at least a metal oxide semiconductor (MOS) transistor 36, the circuit blocks being covered on top with a protective film 41 to protect the circuits. A plurality of bumps 23a, 23b, 23c are formed, at least via the protective film 41, only on circuit blocks whose current-carrying ability and threshold voltage do not satisfy predetermined values and which are in need of performance enhancement. The bumps 23a, 23b, 23c impose stresses on the MOS transistors 36, increasing the mobility of the MOS transistors 36 and thereby improving the performance of the semiconductor device 20.Type: ApplicationFiled: June 22, 2011Publication date: October 20, 2011Applicant: Panasonic CorporationInventors: Takayuki Yoshida, Kimihito Kuwabara, Takuma Motofuji, Toshiyuki Fukuda
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Patent number: 7985988Abstract: A semiconductor device 20 formed on a semiconductor chip substrate 30 has a plurality of circuit blocks made up of circuits each containing at least a metal oxide semiconductor (MOS) transistor 36, the circuit blocks being covered on top with a protective film 41 to protect the circuits. A plurality of bumps 23a, 23b, 23c are formed, at least via the protective film 41, only on circuit blocks whose current-carrying ability and threshold voltage do not satisfy predetermined values and which are in need of performance enhancement. The bumps 23a, 23b, 23c impose stresses on the MOS transistors 36, increasing the mobility of the MOS transistors 36 and thereby improving the performance of the semiconductor device 20.Type: GrantFiled: September 11, 2007Date of Patent: July 26, 2011Assignee: Panasonic CorporationInventors: Takayuki Yoshida, Kimihito Kuwabara, Takuma Motofuji, Toshiyuki Fukuda
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Publication number: 20110115085Abstract: In a semiconductor device of the present invention, semiconductor chips are stacked in multi-layers. Each of the semiconductor chip includes: through vias extending through a top main surface thereof to a bottom surface opposite to the top main surface; a circuit element surface formed on the top main surface; pads arranged on the circuit element surface; bumps formed on the pads; and via pads, formed on the bottom surface thereof, to which the bumps of its upper semiconductor chip are joined, and positions at which the bumps of each of the semiconductor chips are respectively arranged are different from those at which the bumps of its upper semiconductor chip are arranged.Type: ApplicationFiled: January 21, 2011Publication date: May 19, 2011Applicant: PANASONIC CORPORATIONInventor: Kimihito KUWABARA
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Publication number: 20110079902Abstract: A semiconductor device has a wiring substrate provided with an external connecting terminal on a lower surface, a semiconductor chip mounted onto an upper surface of the wiring substrate, a cap-shaped heat dissipation member arranged on the upper surface of the wiring substrate so as to cover the semiconductor chip, a fixing pin for fixing the heat dissipation member onto the upper surface of the wiring substrate, and a heat transfer material sandwiched between a lower surface of the heat dissipation member just above the semiconductor chip and the upper surface of the semiconductor chip.Type: ApplicationFiled: July 30, 2010Publication date: April 7, 2011Inventors: Takeshi SAKAMOTO, Katsumi Otani, Kimihito Kuwabara
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Publication number: 20090267217Abstract: A semiconductor device (20) in which a semiconductor element (2) is mounted on one of a front side and a back side of a wiring board (3), and a plurality of lands (9) (23) for external connection are provided on the other side of the wiring board, the land (9) (23) including a land terminal (10) (24) formed on the wiring board and a spherical solder ball (11) (25) formed on the land terminal, wherein a first land (23) immediately below an outer end corner (B) of the semiconductor element (2) is larger in size than the other lands (9).Type: ApplicationFiled: June 29, 2009Publication date: October 29, 2009Applicant: Panasonic CorporationInventor: Kimihito Kuwabara
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Publication number: 20090218671Abstract: In a semiconductor device of the present invention, semiconductor chips are stacked in multi-layers. Each of the semiconductor chip includes: through vias extending through a top main surface thereof to a bottom surface opposite to the top main surface; a circuit element surface formed on the top main surface; pads arranged on the circuit element surface; bumps formed on the pads; and via pads, formed on the bottom surface thereof, to which the bumps of its upper semiconductor chip are joined, and positions at which the bumps of each of the semiconductor chips are respectively arranged are different from those at which the bumps of its upper semiconductor chip are arranged.Type: ApplicationFiled: March 2, 2009Publication date: September 3, 2009Inventor: Kimihito Kuwabara
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Publication number: 20080061324Abstract: A semiconductor device 20 formed on a semiconductor chip substrate 30 has a plurality of circuit blocks made up of circuits each containing at least a metal oxide semiconductor (MOS) transistor 36, the circuit blocks being covered on top with a protective film 41 to protect the circuits. A plurality of bumps 23a, 23b, 23c are formed, at least via the protective film 41, only on circuit blocks whose current-carrying ability and threshold voltage do not satisfy predetermined values and which are in need of performance enhancement. The bumps 23a, 23b, 23c impose stresses on the MOS transistors 36, increasing the mobility of the MOS transistors 36 and thereby improving the performance of the semiconductor device 20.Type: ApplicationFiled: September 11, 2007Publication date: March 13, 2008Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Takayuki Yoshida, Kimihito Kuwabara, Takuma Motofuji, Toshiyuki Fukuda
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Publication number: 20070132090Abstract: A semiconductor device (20) in which a semiconductor element (2) is mounted on one of a front side and a back side of a wiring board (3), and a plurality of lands (9)(23) for external connection are provided on the other side of the wiring board, the land (9)(23) including a land terminal (10)(24) formed on the wiring board and a spherical solder ball (11)(25) formed on the land terminal, wherein a first land (23) immediately below an outer end corner (B) of the semiconductor element (2) is larger in size than the other lands (9).Type: ApplicationFiled: November 13, 2006Publication date: June 14, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Kimihito Kuwabara
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Publication number: 20070108532Abstract: It is possible to realize the following package structure. That is, a structure for applying a stress to a channel region is provided for a semiconductor chip itself. In a package manufacturing process, a low thermal expansion coefficient film is formed on a circuit face of an Si chip. Thus, distribution and magnitude of a desired stress can be secured for a channel region of a MOSFET in a mounted chip even after performance of the package manufacturing process. As a result, a mobility is increased and current driving power is enhanced.Type: ApplicationFiled: November 13, 2006Publication date: May 17, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Harafuji, Kimihito Kuwabara
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Publication number: 20070072405Abstract: There is provided a semiconductor device in which the junction strength of land portions and external terminals is increased, the disconnection of the external terminal is surely prevented, and the connection reliability is ensured over an extended period of time. An insulating resin layer which insulates metal wires from one another is formed on a semiconductor element, an end portion of the metal wire is connected to an electrode on the semiconductor element, the other end portion of the metal wire is connected to an external terminal to form a land, the entire surface of the semiconductor element except the connecting portions of the lands is covered with a surface-layer resin layer, and a projection is provided on the top surface of a land portion of at least one of the lands. Because of this, after their soldering, the external terminal holds the perimeter of the projection on the land portion, so that the external terminal can be surely connected to the land portion.Type: ApplicationFiled: November 29, 2006Publication date: March 29, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kazuyuki Kainou, Masatoshi Yagoh, Kimihito Kuwabara, Katsumi Ohtani
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Patent number: 7164208Abstract: There is provided a semiconductor device in which the junction strength of land portions and external terminals is increased, the disconnection of the external terminal is surely prevented, and the connection reliability is ensured over an extended period of time. An insulating resin layer which insulates metal wires from one another is formed on a semiconductor element, an end portion of the metal wire is connected to an electrode on the semiconductor element, the other end portion of the metal wire is connected to an external terminal to form a land, the entire surface of the semiconductor element except the connecting portions of the lands is covered with a surface-layer resin layer, and a projection is provided on the top surface of a land portion of at least one of the lands. Because of this, after their soldering, the external terminal holds the perimeter of the projection on the land portion, so that the external terminal can be surely connected to the land portion.Type: GrantFiled: January 19, 2005Date of Patent: January 16, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazuyuki Kainou, Masatoshi Yagoh, Kimihito Kuwabara, Katsumi Ohtani
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Publication number: 20050167832Abstract: There is provided a semiconductor device in which the junction strength of land portions and external terminals is increased, the disconnection of the external terminal is surely prevented, and the connection reliability is ensured over an extended period of time. An insulating resin layer which insulates metal wires from one another is formed on a semiconductor element, an end portion of the metal wire is connected to an electrode on the semiconductor element, the other end portion of the metal wire is connected to an external terminal to form a land, the entire surface of the semiconductor element except the connecting portions of the lands is covered with a surface-layer resin layer, and a projection is provided on the top surface of a land portion of at least one of the lands. Because of this, after their soldering, the external terminal holds the perimeter of the projection on the land portion, so that the external terminal can be surely connected to the land portion.Type: ApplicationFiled: January 19, 2005Publication date: August 4, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kazuyuki Kainou, Masatoshi Yagoh, Kimihito Kuwabara, Katsumi Ohtani
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Patent number: 6371017Abstract: The temperature of a portion that belongs to a stencil and is located in the vicinity of a portion retaining a printing paste is increased to reduce the viscosity of printing paste that adheres to the portion retaining the printing paste, thereby allowing the printing paste to be easily separated from the retaining portion for the achievement of easy printing on an object on which a print is to be formed.Type: GrantFiled: November 9, 2000Date of Patent: April 16, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Osamu Yamazaki, Kimihito Kuwabara, Kazumi Ishimoto, Toshiaki Yamauchi, Toshinori Mimura
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Patent number: 6230619Abstract: The temperature of a portion that belongs to a stencil and is located in the vicinity of a portion retaining a printing paste is increased to reduce the viscosity of printing paste that adheres to the portion retaining the printing paste, thereby allowing the printing paste to be easily separated from the retaining portion for the achievement of easy printing on an object on which a print is to be formed.Type: GrantFiled: November 16, 1998Date of Patent: May 15, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Osamu Yamazaki, Kimihito Kuwabara, Kazumi Ishimoto, Toshiaki Yamauchi, Toshinori Mimura
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Patent number: 5715990Abstract: The present invention provides a reflow apparatus and method effective to make constant the internal gas flow direction in a heating section within a reflow furnace. A circulating gas path is formed in a heating unit which collects and causes the gas to flow from a sirocco fan, up the rear side of the heating unit and then down towards a circuit board moving along a transfer path at the front side of the heating unit. Moreover, a plurality of straightening plates are arranged above the transfer path of the heating unit so as to guide the hot gas, which is flowing forwardly downwardly toward the circuit board moving along the transfer path. A blow-down nozzle is provided and includes a plurality of plates aligned in rows in the transferring direction of the circuit boards. The plates have an inverse U-shaped cross section. The blow-down nozzle is arranged below the straightening plates to cause the vertical hot gas flows to flow uniformly over the whole surface of the circuit board.Type: GrantFiled: February 14, 1996Date of Patent: February 10, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masahiro Taniguchi, Youichi Nakamura, Kazumi Ishimoto, Kimihito Kuwabara, Toshinori Mimura, Kurayasu Hamasaki, Kenichi Nakano, Manabu Ando
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Patent number: 5579981Abstract: A reflow apparatus includes a reflow furnace. A transfer device holds and transfers printed circuit boards with to-be-reflowed electronic components thereon from an inlet to an outlet of the furnace within the furnace. A plurality of adjusting/circulating sections separate an ambient gas for heating the printed circuit boards into predetermined temperature regions in the furnace in which the ambient gas is circulated in a heated state. A feed port is formed in the furnace to feed the ambient gas into the furnace under pressure. Residence parts each provided between adjacent adjusting/circulating sections regulate the amount of the ambient gas when the ambient gas, after having been sent to and heated in the adjusting/circulating section adjacent to the feed port, is circulated and sequentially moved to the adjusting/circulating sections at the inlet or the outlet and finally flows out through the inlet or outlet into atmosphere.Type: GrantFiled: January 12, 1995Date of Patent: December 3, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nobuya Matsumura, Kazumi Ishimoto, Yoichi Nakamura, Kurayasu Hamasaki, Kimihito Kuwabara, Masahiro Taniguchi
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Patent number: 5524812Abstract: The present invention provides a reflow apparatus and method effective to make constant the internal gas flow direction in a heating section within a reflow furnace. A circulating gas path is formed in a heating unit which collects and causes the gas to flow from a sirocco fan, up the rear side of the heating unit and then down towards a circuit board moving along a transfer path at the front side of the heating unit. Moreover, a plurality of straightening plates are arranged above the transfer path of the heating unit so as to guide the hot gas, which is flowing forwardly downwardly toward the circuit board moving along the transfer path. A blow-down nozzle is provided and includes a plurality of plates aligned in rows in the transferring direction of the circuit boards. The plates have an inverse U-shaped cross section. The blow-down nozzle is arranged below the straightening plates to cause the vertical hot gas flows to flow uniformly over the whole surface of the circuit board.Type: GrantFiled: May 17, 1995Date of Patent: June 11, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masahiro Taniguchi, Youichi Nakamura, Kazumi Ishimoto, Kimihito Kuwabara, Toshinori Mimura, Kurayasu Hamasaki, Kenichi Nakano, Manabu Ando
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Patent number: 5472135Abstract: The present invention provides a reflow apparatus and method effective to make constant the internal gas flow direction in a heating section within a reflow furnace. A circulating gas path is formed in a heating unit which collects and causes the gas to flow from a sirocco fan, up the rear side of the heating unit and then down towards a circuit board moving along a transfer path at the front side of the heating unit. Moreover, a plurality of straightening plates are arranged above the transfer path of the heating unit so as to guide the hot gas, which is flowing forwardly downwardly toward the circuit board moving along the transfer path. A blow-down nozzle is provided and includes a plurality of plates aligned in rows in the transferring direction of the circuit boards. The plates have an inverse U-shaped cross section. The blow-down nozzle is arranged below the straightening plates to cause the vertical hot gas flows to flow uniformly over the whole surface of the circuit board.Type: GrantFiled: November 16, 1993Date of Patent: December 5, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masahiro Taniguchi, Youichi Nakamura, Kazumi Ishimoto, Kimihito Kuwabara, Toshinori Mimura, Kurayasu Hamasaki, Kenichi Nakano, Manabu Ando