Patents by Inventor Kimikazu Hazumi

Kimikazu Hazumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230296268
    Abstract: A first passage forming member and a second passage forming member each include: a rib portion including a first wall portion constituting an end in a first direction of the first passage, a second wall portion constituting an end in the first direction of the second passage, and a third wall portion separating the first passage and the second passage adjacent to each other in a second direction from each other; a board being in contact with an end in a third direction of the rib portion, and separating a first connection passage and a second connection passage from each other; a first blocking portion installed at the end of the rib portion, to block between the first passage and the second connection passage; and a second blocking portion installed at the end of the rib portion, to block between the second passage and the first connection passage.
    Type: Application
    Filed: August 21, 2020
    Publication date: September 21, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tomoya WATANABE, Tsuyoshi TSUBOUCHI, Shunsaburo OKAWA, Hajime SOTOKAWA, Kimikazu HAZUMI
  • Patent number: 8012787
    Abstract: The manufacturing method includes: forming a P-type silicon substrate and a high-concentration N-type diffusion layer, in which an N-type impurity is diffused in a first concentration, on an entire surface at a light-incident surface side; forming an etching resistance film on the high-concentration N-type diffusion layer and forming fine pores at a predetermined position within a recess forming regions on the etching resistance film; forming recesses by etching the silicon substrate around a forming position of the fine pores, so as not to leave the high-concentration N-type diffusion layer within the recess forming region; forming the low-concentration N-type diffusion layer, in which an N-type impurity is diffused in a second concentration that is lower than the first concentration, on a surface on which the recesses are formed; and forming a grid electrode in an electrode forming region at a light-incident surface side of the silicon substrate.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: September 6, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masato Yonezawa, Kimikazu Hazumi, Akihiro Takami, Hiroaki Morikawa, Kunihiko Nishimura
  • Publication number: 20110053310
    Abstract: The manufacturing method includes: forming a P-type silicon substrate and a high-concentration N-type diffusion layer, in which an N-type impurity is diffused in a first concentration, on an entire surface at a light-incident surface side; forming an etching resistance film on the high-concentration N-type diffusion layer and forming fine pores at a predetermined position within a recess forming regions on the etching resistance film; forming recesses by etching the silicon substrate around a forming position of the fine pores, so as not to leave the high-concentration N-type diffusion layer within the recess forming region; forming the low-concentration N-type diffusion layer, in which an N-type impurity is diffused in a second concentration that is lower than the first concentration, on a surface on which the recesses are formed; and forming a grid electrode in an electrode forming region at a light-incident surface side of the silicon substrate.
    Type: Application
    Filed: April 30, 2008
    Publication date: March 3, 2011
    Applicant: Mitsubishi Electric Corporation
    Inventors: Masato Yonezawa, Kimikazu Hazumi, Akihiro Takami, Hiroaki Morikawa, Kunihiko Nishimura