Abstract: A low-voltage output driving circuit capable of preventing the generation of leakage current. The circuit includes a transfer gate GT installed between the output S.sub.2 of a first CMOS inverter INV.sub.C1 and the node S.sub.1 at the gate of an MOS transistor PT.sub.3 for active pull-up. At the same time, a reference voltage V.sub.REF and a voltage level V.sub.OUT, which corresponds to the voltage level of the output line of the signal S.sub.OUT, are compared by a comparator CMP. When the voltage V.sub.OUT is lower than the reference voltage V.sub.REF, the transfer gate GT is set to the ON state, and the output of the first CMOS inverter INV.sub.C1 is sent to the gate of the transistor PT.sub.3 for active pull-up. The comparator CMP is installed so that when the voltage level V.sub.OUT is higher than the reference voltage V.sub.REF, the output of the first CMOS inverter INV.sub.C1 is prevented from reaching the gate of the transistor PT.sub.3 for active pull-up.