Abstract: In one embodiment, a protection circuit in a semiconductor device includes first and second transistors including gates electrically connected to a first node, and connected in series to each other between the first and second lines, third and fourth transistors including gates electrically connected to a second node between the first and second transistors, and connected in series to each other between the first and second lines, and a fifth transistor including a gate electrically connected to a third node between the third and fourth transistors, and provided between the second node and the second line. The protection circuit further includes an arithmetic circuit configured to perform calculation using a first signal received from the second node to output a second signal, and a sixth transistor configured to receive the second signal to output a control signal to the arithmetic circuit.

Abstract: In one embodiment, a protection circuit in a semiconductor device includes first and second transistors including gates electrically connected to a first node, and connected in series to each other between the first and second lines, third and fourth transistors including gates electrically connected to a second node between the first and second transistors, and connected in series to each other between the first and second lines, and a fifth transistor including a gate electrically connected to a third node between the third and fourth transistors, and provided between the second node and the second line. The protection circuit further includes an arithmetic circuit configured to perform calculation using a first signal received from the second node to output a second signal, and a sixth transistor configured to receive the second signal to output a control signal to the arithmetic circuit.

Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data storage circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data output circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data output circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data storage circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data output circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data output circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

Abstract: A semiconductor memory device includes a memory cell array, word line, row decoder, bit line, sense amplifier, dummy cell array, dummy bit line, sense amplifier activation circuit, and signal interconnection. The word line is connected to memory cells arrayed in the column direction. The row decoder is connected to the word line. The bit line is connected to memory cells arrayed in the row direction. The sense amplifier is connected to the bit line. Dummy cells are arrayed in the row direction between the row decoder and the memory cell array. The dummy bit line is connected to the dummy cells. The sense amplifier activation circuit transmits a sense start signal for setting a sense start timing to the sense amplifier through the signal interconnection. In this arrangement, the signal delay of the word line is set to be equal to that of the signal interconnection.

Abstract: A basic unit block has a plurality of memory cells, a local bit line pair connected to the plurality of memory cells, and a bit line precharge circuit and a transfer gate switch circuit which are connected to the local bit line pair. The local bit line pairs in a plurality of basic unit blocks are connected to a global bit line pair via the transfer gate switch circuit. The global bit line pair constitutes a layered bit line structure together with the local bit line pair. The global bit line pair is laid out to extend in the same direction and is twisted once or more in this extending direction.

Abstract: A semiconductor memory device includes a memory cell array, word line, row decoder, bit line, sense amplifier, dummy cell array, dummy bit line, sense amplifier activation circuit, and signal interconnection. The word line is connected to memory cells arrayed in the column direction. The row decoder is connected to the word line. The bit line is connected to memory cells arrayed in the row direction. The sense amplifier is connected to the bit line. Dummy cells are arrayed in the row direction between the row decoder and the memory cell array. The dummy bit line is connected to the dummy cells. The sense amplifier activation circuit transmits a sense start signal for setting a sense start timing to the sense amplifier through the signal interconnection. In this arrangement, the signal delay of the word line is set to be equal to that of the signal interconnection.

Abstract: A basic unit block has a plurality of memory cells, a local bit line pair connected to the plurality of memory cells, and a bit line precharge circuit and a transfer gate switch circuit which are connected to the local bit line pair. The local bit line pairs in a plurality of basic unit blocks are connected to a global bit line pair via the transfer gate switch circuit. The global bit line pair constitutes a layered bit line structure together with the local bit line pair. The global bit line pair is laid out to extend in the same direction and is twisted once or more in this extending direction.

Abstract: At a Power-On time, a read potential is generated by a VBP generating circuit (Power-On). The read potential is applied as VBP to a program element to check the state of the program element. The read potential is produced from, e.g. a logic power supply potential. At a program time, a program potential is generated by a VBP generating circuit (Program). The program potential is supplied, for example, from the outside of the chip. The program potential is applied as VBP to the program element. While the read/program potential is being output, the gate of a barrier transistor is supplied with VBT, e.g. a power supply potential.

Abstract: At a Power-On time, a read potential is generated by a VBP generating circuit (Power-On). The read potential is applied as VBP to a program element to check the state of the program element. The read potential is produced from, e.g. a logic power supply potential. At a program time, a program potential is generated by a VBP generating circuit (Program). The program potential is supplied, for example, from the outside of the chip. The program potential is applied as VBP to the program element. While the read/program potential is being output, the gate of a barrier transistor is supplied with VBT, e.g. a power supply potential.

Abstract: To suppress the power-on current flowing when power is tuned on in the circuit which feeds precharging current to the bit lines of the banks in a synchronous DRAM comprising a multi-bank structure. The device comprises a plurality of bank circuits BKi which are all of the same structure, wherein the bit line precharging power supply lines which the respective bank circuits have are connected in common, a first precharging power supply circuit which has its output node connected to the precharging power supply line and starts its precharging current feed operation when the power supply in the DRAM chip is turned on, and a second precharging power supply circuit which has its output node connected to the precharging power supply line and starts its precharging current feed operation after the bit line has been raised to a predetermined potential by the precharging current of the first precharging power supply circuit.

Abstract: A read-write semiconductor memory comprises a first data input buffer which takes in external data and which has a pair of signal output nodes for outputting a pair of signals corresponding to the taken-in data, a pair of signal lines connected to a pair of signal output nodes of the first data input buffer, and second data input buffers which are connected to the pair of signal lines and which have internal data set according to the signals on the pair of signal lines.

Abstract: The parity cell arrays are placed between the ordinary cell arrays and a second peripheral circuit. Data signal lines are provided between the ordinary cell arrays, between the ordinary cell arrays and the parity cell arrays, and between the parity cell arrays. These data signal lines are connected to read-write lines via data signal-line amplifier circuits. These data column-line amplifier circuits have almost the same construction. The data signal-line control circuit activates the data signal-line amplifier circuits during a write and a read operation to enable data transfer between the data signal lines and the read-write lines.

Abstract: There is an R-S flip-flop circuit having a threshold voltage of a first value. An input terminal of a Schmitt trigger circuit having a second threshold voltage of a lower value than the first value and a third threshold voltage of a higher value than the first value is connected to an output terminal of the R-S flip-flop circuit.