Abstract: Disclosed herein is a misjudgment correction circuit, including, an edge detection section configured to detect, in a binarized full addition signal obtained by adding first and second signals of the same or opposite polarity, edges at which the logic value of the binarized signal changes, a push-pull signal acquisition section configured to acquire a binarized push-pull signal obtained by subtracting the second signal from the first signal, a majority decision calculation section configured to acquire, in chronologic order, a plurality of logic values of the push-pull signal between the two adjacent edges so as to determine, by a majority decision, the more numerous of the two logic values, and a wave correction section configured to correct the push-pull signal between the edges to the more numerous logic value determined by the majority decision calculation section.

Abstract: A comparator includes a variable-gain amplifier circuit configured to vary an amplitude of an input signal by changing a gain in accordance with a control signal, and a comparison section configured to compare a slice level interlocked with a signal level received from the variable-gain amplifier circuit with an output signal received from the variable-gain amplifier circuit and generate an output signal in accordance with a comparison result.

Abstract: A wobble signal extraction circuit includes: an RF signal component acquiring portion for acquiring an RF signal component from at least one of first and second signals received by two light receiving portions, the two light receiving portions being obtained through division in halves with a direction along which each track of an optical recording medium extends as a boundary; a wobble signal acquiring portion for acquiring a wobble signal by subtracting the second signal from the first signal; an RF signal component binarizing portion for binarizing the RF signal component; a wobble signal binarizing portion for binarizing the wobble signal; and an exclusive OR arithmetically operating portion for arithmetically operating an exclusive OR of the binarized RF signal component and the binarized wobble signal; wherein balances between amplitudes of the first and second signals are detected based on an arithmetic operation result obtained in the exclusive OR arithmetically operating portion.

Abstract: A comparator includes a variable-gain amplifier circuit configured to vary an amplitude of an input signal by changing a gain in accordance with a control signal, and a comparison section configured to compare a slice level interlocked with a signal level received from the variable-gain amplifier circuit with an output signal received from the variable-gain amplifier circuit and generate an output signal in accordance with a comparison result.

Abstract: Disclosed herein is a misjudgment correction circuit, including, an edge detection section configured to detect, in a binarized full addition signal obtained by adding first and second signals of the same or opposite polarity, edges at which the logic value of the binarized signal changes, a push-pull signal acquisition section configured to acquire a binarized push-pull signal obtained by subtracting the second signal from the first signal, a majority decision calculation section configured to acquire, in chronologic order, a plurality of logic values of the push-pull signal between the two adjacent edges so as to determine, by a majority decision, the more numerous of the two logic values, and a wave correction section configured to correct the push-pull signal between the edges to the more numerous logic value determined by the majority decision calculation section.

Abstract: A wobble signal extraction circuit includes: an RF signal component acquiring portion for acquiring an RF signal component from at least one of first and second signals received by two light receiving portions, the two light receiving portions being obtained through division in halves with a direction along which each track of an optical recording medium extends as a boundary; a wobble signal acquiring portion for acquiring a wobble signal by subtracting the second signal from the first signal; an RF signal component binarizing portion for binarizing the RF signal component; a wobble signal binarizing portion for binarizing the wobble signal; and an exclusive OR arithmetically operating portion for arithmetically operating an exclusive OR of the binarized RF signal component and the binarized wobble signal; wherein balances between amplitudes of the first and second signals are detected based on an arithmetic operation result obtained in the exclusive OR arithmetically operating portion.

Abstract: A PLL circuit and an information reproduction apparatus able to reduce an influence of erroneous detection even when erroneous detection of a frequency comparator occurs and able to realize stable and high speed frequency lock-in, having a frequency comparator 25 fetching a zero cross signal ZC in synchronization with clocks CLKA to CLKC from a VCO 23 and observing from which phase to which phase an edge of the zero cross changed in synchronization with the clock CLKA and thereby detecting high/low of the frequency as frequency error and outputting an up signal UP or a down signal DOWN, an integration circuit 26 integrating the signal UP or DOWN, a comparator 27 receiving the integrated up signal UP or down signal DOWN, judging a direction of the frequency error, and outputting three signals of UPM, DOWNM, and NONM, and a gain adjustment circuit 28 determining whether or not the signal is to be output or determining a feedback gain from the pattern of a sequence of the signals UPM, DOWNM, and NONM, and output

Abstract: A wobble PLL circuit in an optical disk apparatus of the present invention is provided with a modulation and defect detector for measuring a fluctuation between adjoining cycles or a fluctuation of a one cycle interval included in an output signal of the phase comparator, and, if the measurement value exceeds a predetermined threshold value, assuming the measured value as a modulation portion or a defect and masking a feedback signal to a voltage controlled oscillator. As a result, a position of a phase window can be set accuracy, a normal phase comparison can be recognized, and a phase comparison result due to the defect can be masked accuracy, also.

Abstract: A PLL circuit functioning as a clock recovery circuit in a tape recording and playback apparatus employing the PRML method has a level determining circuit for detecting that head output level (signal level) is at or lower than a certain level during track crossing for a high-speed search, and effects a hold on a loop filter according to a level determination output to thereby hold PLL operation, whereby the PLL behavior is not disturbed by a noise component occurring during track crossing. Thus, it is possible to stabilize search operation and increase the design margin.

Abstract: To provide an asymmetry correcting circuit capable of canceling an asymmetry simultaneously with quantization in an ADC and utilizing the dynamic range of the ADC effectively, and also to provide an information reproducing apparatus using such a correcting circuit.

Abstract: A nonlinearity compensation circuit is disclosed which includes an inverse hyperbolic function generation circuit for converting differential currents corresponding to input signals in+ and in− into differential voltages which increase in proportion to an inverse hyperbolic function, an offset provision circuit for providing an offset corresponding to control signals c+ and c− to the differential voltages outputted from the inverse hyperbolic function generation circuit and a hyperbolic function generation circuit for converting the differential voltages to which the offset has been provided by the offset provision circuit into signals which increase in proportion to a hyperbolic function and outputting the resulting signals as output signals out+ and out−. Consequently, compensation for the nonlinearity such as second order distortion can be performed for the read signal from a recording medium.

Abstract: A PLL (phase-locked loop) circuit is configured with a phase-error detection circuit comprises the following: a provisional judge circuit for provisionally judging a data signal being input to an A/D converter into three levels of 1, 0, and −1; a pattern detector which, among data signals being input in accordance with a result of the provisional judgment, checks a transition pattern ranging from a data signal that precedes one clock cycle to the actually present data signal, and then, when a specific pattern is detected, instructs a selector to select output data from the A/D converter; and the selector which, in compliance with instruction from the pattern detector, selects phase-error data from data signals output from the A/D converter, and then converts the selected phase-error data into an electric current before externally delivering it as an error-current.

Abstract: To provide an asymmetry correcting circuit capable of canceling an asymmetry simultaneously with quantization in an ADC and utilizing the dynamic range of the ADC effectively, and also to provide an information reproducing apparatus using such a correcting circuit.

Abstract: A nonlinearity compensation circuit is disclosed which includes an inverse hyperbolic function generation circuit for converting differential currents corresponding to input signals in+ and in− into differential voltages which increase in proportion to an inverse hyperbolic function, an offset provision circuit for providing an offset corresponding to control signals c+ and c− to the differential voltages outputted from the inverse hyperbolic function generation circuit and a hyperbolic function generation circuit for converting the differential voltages to which the offset has been provided by the offset provision circuit into signals which increase in proportion to a hyperbolic function and outputting the resulting signals as output signals out+ and out−. Consequently, compensation for the nonlinearity such as second order distortion can be performed for the read signal from a recording medium.

Abstract: A PLL circuit functioning as a clock recovery circuit in a tape recording and playback apparatus employing the PRYL method has a level determining circuit for detecting that head output level (signal level) is at or lower than a certain level during track crossing for a high-speed search, and effects a hold on a loop filter according to a level determination output to thereby hold PLL operation, whereby the PLL behavior is not disturbed by a noise component occurring during track crossing. Thus, it is possible to stabilize search operation and increase the design margin.