Patents by Inventor Kimimori Hamada
Kimimori Hamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9640651Abstract: A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.Type: GrantFiled: October 6, 2014Date of Patent: May 2, 2017Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Hidefumi Takaya, Jun Saito, Akitaka Soeno, Kimimori Hamada, Shoji Mizuno, Sachiko Aoi, Yukihiko Watanabe
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Patent number: 9627248Abstract: An insulating gate type semiconductor device being capable of easily depleting an outer periphery region is provided. The insulating gate type semiconductor device includes: first to fourth outer periphery trenches formed in a front surface of a semiconductor substrate; insulating layers located in the outer periphery trenches; fifth semiconductor regions being of a second conductive type and formed in ranges exposed to bottom surfaces of the outer periphery trenches; and a connection region connecting the fifth semiconductor region exposed to the bottom surface of the second outer periphery trench to the fifth semiconductor region exposed to the bottom surface of the third outer periphery trench. A clearance between the second and third outer periphery trenches is wider than each of a clearance between the first and second outer periphery trenches and a clearance between the third and fourth outer periphery trenches.Type: GrantFiled: February 5, 2015Date of Patent: April 18, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Jun Saito, Kimimori Hamada, Akitaka Soeno, Hidefumi Takaya, Sachiko Aoi, Toshimasa Yamamoto
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Publication number: 20170012122Abstract: A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.Type: ApplicationFiled: October 6, 2014Publication date: January 12, 2017Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Hidefumi TAKAYA, Jun SAITO, Akitaka SOENO, Kimimori HAMADA, Shoji MIZUNO, Sachiko AOI, Yukihiko WATANABE
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Publication number: 20170011952Abstract: An insulating gate type semiconductor device being capable of easily depleting an outer periphery region is provided. The insulating gate type semiconductor device includes: first to fourth outer periphery trenches formed in a front surface of a semiconductor substrate; insulating layers located in the outer periphery trenches; fifth semiconductor regions being of a second conductive type and formed in ranges exposed to bottom surfaces of the outer periphery trenches; and a connection region connecting the fifth semiconductor region exposed to the bottom surface of the second outer periphery trench to the fifth semiconductor region exposed to the bottom surface of the third outer periphery trench. A clearance between the second and third outer periphery trenches is wider than each of a clearance between the first and second outer periphery trenches and a clearance between the third and fourth outer periphery trenches.Type: ApplicationFiled: February 5, 2015Publication date: January 12, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Jun SAITO, Kimimori HAMADA, Akitaka SOENO, Hidefumi TAKAYA, Sachiko AOI, Toshimasa YAMAMOTO
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Patent number: 8933483Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.Type: GrantFiled: November 7, 2013Date of Patent: January 13, 2015Assignee: Toyota Jidosha Kabushiki KaishaInventors: Hidefumi Takaya, Kimimori Hamada, Yuji Nishibe
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Patent number: 8809986Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current. In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.Type: GrantFiled: May 29, 2009Date of Patent: August 19, 2014Assignee: Toyota Jidosha Kabushiki KaishaInventors: Hidefumi Takaya, Kimimori Hamada, Yuji Nishibe
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Publication number: 20140054688Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.Type: ApplicationFiled: November 7, 2013Publication date: February 27, 2014Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hidefumi TAKAYA, Kimimori HAMADA, Yuji NISHIBE
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Publication number: 20120068296Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.Type: ApplicationFiled: May 29, 2009Publication date: March 22, 2012Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hidefumi Takaya, Kimimori Hamada, Yuji Nishibe
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Publication number: 20120007222Abstract: The present specification provides a method of efficiently manufacturing diodes in which recovery surge voltage is hardly generated. The method manufactures a diode including a high concentration n-type semiconductor layer, a medium concentration n-type semiconductor layer formed on the high concentration n-type semiconductor layer, a low concentration n-type semiconductor layer formed on the medium concentration n-type semiconductor layer, and a p-type semiconductor layer formed on the low concentration n-type semiconductor layer. This manufacturing method includes growing the low concentration n-type semiconductor layer on an n-type semiconductor substrate by epitaxial growth, wherein a concentration of n-type impurities in the low concentration n-type semiconductor layer is lower than that in the n-type semiconductor substrate, and forming the high concentration n-type semiconductor layer by injecting n-type impurities to a lower surface of the n-type semiconductor substrate.Type: ApplicationFiled: September 23, 2011Publication date: January 12, 2012Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Tadashi MISUMI, Kimimori HAMADA
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Patent number: 8076718Abstract: The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.Type: GrantFiled: September 28, 2005Date of Patent: December 13, 2011Assignees: Toyota Jidosha Kabushiki Kaisha, Denso CorporationInventors: Hidefumi Takaya, Kimimori Hamada, Kyosuke Miyagi, Yasushi Okura, Akira Kuroyanagi, Norihito Tokura
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Patent number: 7999312Abstract: A semiconductor 100 has a P? body region and an N? drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P? body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P?? diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P? body region and the P diffusion region, is formed. The P?? diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P?? diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.Type: GrantFiled: January 26, 2007Date of Patent: August 16, 2011Assignee: Toyota Jidosha Kabushiki KaishaInventors: Hidefumi Takaya, Kimimori Hamada, Kyosuke Miyagi
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Publication number: 20100224932Abstract: A semiconductor 100 has a P? body region and an N? drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P? body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P?? diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P? body region and the P diffusion region, is formed. The P?? diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P?? diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.Type: ApplicationFiled: January 26, 2007Publication date: September 9, 2010Inventors: Hidefumi Takaya, Kimimori Hamada, Kyosuke Miyagi
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Patent number: 7470953Abstract: The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P? body region 41, and N? drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 incorporates the gate electrode 22. A P floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.Type: GrantFiled: October 6, 2004Date of Patent: December 30, 2008Assignees: Toyota Jidosha Kabushiki Kaisha, Denso CorporationInventors: Hidefumi Takaya, Kimimori Hamada, Akira Kuroyanagi, Yasushi Okura, Norihito Tokura
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Publication number: 20080087951Abstract: The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.Type: ApplicationFiled: September 28, 2005Publication date: April 17, 2008Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hidefumi Takaya, Kimimori Hamada, Kyosuke Miyagi, Yasushi Okura, Akira Kuroyanagi, Norihiko Tokura
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Publication number: 20080087949Abstract: A p-type epitaxial layer is formed on an n+-type substrate and then a buried n-type region is formed at a boundary between the n+-type substrate and the p-type epitaxial layer by ion implantation. Subsequently, a trench is formed so as to reach the n+-type substrate, passing through the p-type epitaxial layer and the buried n-type region. Then, a gate electrode is formed so as to deeply extend into the trench, i.e. to a position opposed to the buried n-type region. In a vertical MOSFET with this structure, when a positive voltage is applied to the gate electrode, an accumulation layer with a low resistance is formed in the buried n-type region, thereby reducing an on-resistance.Type: ApplicationFiled: September 12, 2007Publication date: April 17, 2008Applicants: NEC ELECTRONICS CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Michiaki MARUOKA, Kimimori HAMADA, Hidefumi TAKAYA
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Publication number: 20060289928Abstract: The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P? body region 41, and N? drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.Type: ApplicationFiled: October 6, 2004Publication date: December 28, 2006Inventors: Hidefumi Takaya, Kimimori Hamada, Akira Kuroyanagi, Yasushi Okura, Norihito Tokura
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Patent number: 6803628Abstract: A power semiconductor device having a low on-resistance and a high breakdown ruggedness is disclosed. Trench regions formed so as to contact trench gates via gate-insulating films are connected by emitter regions so as to form a ladder-shaped configuration. The emitter regions are formed at a shallower depth than the trench regions. Therefore, the resistance in portions of the body that are near the interfaces with the emitter regions is reduced, and the operation of parasitic transistors formed by the emitter regions, the body, and an epitaxial layer is substantially prevented. As a result, the on-resistance is varied, and the avalanche ruggedness and the latch-up ruggedness are improved.Type: GrantFiled: September 15, 2000Date of Patent: October 12, 2004Assignee: Toyota Jidosha Kabushiki KaishaInventor: Kimimori Hamada