Patents by Inventor Kiminari Yamazoe

Kiminari Yamazoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory control circuit and integrated circuit including branch instruction and detection and operation mode control of a memory
    Patent number: 8484445
    Abstract: A memory control circuit includes a branch detection section to detect a branch instruction from an instruction fetched from a memory unit including a plurality of operation modes, and a mode control section to change an operation mode of the memory unit according to a detection result by the branch detection section. The memory unit includes a plurality of memories, the plurality of operation modes include a normal mode allowing access and a standby mode consuming a lower power than the normal mode, and in response to the detection of a branch instruction from an instruction fetched from any one of the plurality of memories, the mode control section makes standby release of the other memories.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: July 9, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Kiminari Yamazoe
  • MEMORY CONTROL CIRCUIT AND INTEGRATED CIRCUIT INCLUDING BRANCH INSTRUCTION AND DETECTION AND OPERATION MODE CONTROL OF A MEMORY
    Publication number: 20120179926
    Abstract: A memory control circuit includes a branch detection section to detect a branch instruction from an instruction fetched from a memory unit including a plurality of operation modes, and a mode control section to change an operation mode of the memory unit according to a detection result by the branch detection section. The memory unit includes a plurality of memories, the plurality of operation modes include a normal mode allowing access and a standby mode consuming a lower power than the normal mode, and in response to the detection of a branch instruction from an instruction fetched from any one of the plurality of memories, the mode control section makes standby release of the other memories.
    Type: Application
    Filed: March 13, 2012
    Publication date: July 12, 2012
    Applicant: Renesas Electronics Corporation
    Inventor: Kiminari Yamazoe
  • Memory control circuit and integrated circuit including branch instruction detection and operation mode control of a memory
    Patent number: 8161272
    Abstract: The memory unit is compatible with a plurality of operation modes. The plurality of operation modes include the normal mode allowing access and the standby mode consuming a lower power than the normal mode. The branch detection section detects a branch instruction from an instruction fetched from the memory unit by the CPU. The mode control section changes an operation mode of the memory unit according to a detection result by the branch detection section.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: April 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kiminari Yamazoe
  • Memory control circuit and integrated circuit
    Publication number: 20100005251
    Abstract: The memory unit is compatible with a plurality of operation modes. The plurality of operation modes include the normal mode allowing access and the standby mode consuming a lower power than the normal mode. The branch detection section detects a branch instruction from an instruction fetched from the memory unit by the CPU. The mode control section changes an operation mode of the memory unit according to a detection result by the branch detection section.
    Type: Application
    Filed: December 23, 2008
    Publication date: January 7, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Kiminari Yamazoe