Abstract: An interrupt request processing device and method for control of the bus cycle of a microprocessor which implements predetermined wait periods dependent upon a detected wait request. Predetermined wait states, programmable in the microprocessor, are assigned to wait request signals for implementation of a predetermined wait period corresponding to a detected wait request signal, in which the bus cycle is suspended for the predetermined wait period while the signal to be applied to the connected peripheral device is held during access to the peripheral device. After the predetermined wait period is over the bus cycle is unsuspended and the microprocessor is again able to detect wait request signals.

Abstract: A CRT display device with a picture-rearranging circuit in which a display address for accessing a memory to display data stored in the memory is calculated at a high speed by hardware, i.e., a calculator, which counts values from an address counter or a reading or writing address from a microprocessing unit and an offset address generated from the microprocessing unit, the offset address being used to change the picture-arrangement on a display panel.

Abstract: A method for controlling a plurality of memory planes in a writing operation in a display control apparatus of a graphic system, the method including the steps of selectively connecting a plurality of the memory planes to a data bus by using an interface unit; selectively applying a write enable signal to the memory planes from a plane designating unit; applying data to be written to the data bus from a central processing unit; writing the data into the memory planes to which the write enable signal has been applied and which are connected to the data bus; and writing predetermined fixed data into the memory planes to which is the write enable signal has been applied but which are not connected to the data bus.

Abstract: A display system comprises a first image memory storing first image data, a second image memory storing second image data operable independently from the first image memory, a display selection and combination circuit, and two display units. The display selection and combination circuit connected to the first and second image memories is formed such that each of the display units displays a combination of data from the image memories according to a display request. Normally, the display units are cathode ray tubes or liquid crystal displays. Usually, one of the first and second image memories stores character information, such as letters and numerals, and the other stores graphic information, such as figures and curves.

Abstract: A data processing apparatus includes a CPU, a memory, and logic operation hardware. When a predetermined instruction code is identified, the logic operation hardware executes an arithmetic operation using data stored in the memory, while the CPU processes the same data. The logic operation hardware then writes the result of the arithmetic operation instead of the data processed by the CPU.