Abstract: An electrostatic protection device includes a base member formed of a high-resistance semiconductor material. External connecting lands are formed on a first principal surface of the base member along a first direction with a space therebetween. A diode section is formed in the first principal surface of the base member through a semiconductor forming process. The diode section is formed between formation regions of the external connecting lands along the first direction. A high concentration region is a region that has the same polarity as the base member and contains larger amounts of impurities than the base member. The high concentration region is formed in a ring shape enclosing the diode section in a plan view of the base member.

Abstract: According to one embodiment, a semiconductor device includes a p-type semiconductor layer, an n-type source region, an insulator, an n-type semiconductor region, an n-type drain region, a p-type channel region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and an electrode. The source region is provided on a surface of the p-type semiconductor layer. The insulator is provided in a trench formed extending in a thickness direction of the p-type semiconductor layer from the surface of the p-type semiconductor layer. The n-type semiconductor region is provided on the surface of the p-type semiconductor layer between the source region and the insulator. The drain region is provided on the surface of the p-type semiconductor layer between the source region and the n-type semiconductor region and separated from the source region and the n-type semiconductor region.

Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor layer on a major surface thereof. The semiconductor layer is formed to extend in the vertical direction of the major surface of the semiconductor substrate. A stress application layer is provided on either side of the semiconductor layer and applies a stress to the semiconductor layer.

Abstract: A gate electrode is formed on a gate insulator above a semiconductor substrate. Diffused regions are formed in a surface of the semiconductor substrate as sandwiching the gate electrode therebetween. A high-resistance layer is formed in the surface of the semiconductor substrate as electrically connected to the diffused region. A low-resistance layer is formed in the surface of the semiconductor substrate as electrically connected to the high-resistance layer. A drain electrode is connected to the low-resistance layer.

Abstract: A lateral high-breakdown-voltage transistor comprises an n? drain region and an n+ source region formed in a p? silicon substrate, separated from each other, a gate electrode formed on a channel, insulated from the substrate, an n+ drain contact region formed in the drain region, drain wiring electrically connected to the drain region via the drain contact region, a p+ substrate contact region formed in contact with the source region, and source wiring electrically connected to the source region and also connected to the semiconductor layer via the substrate contact region. The transistor is characterized in that the substrate contact regions have respective portions made to be in contact with the source wiring, and accordingly laterally extend from inside the contact surface of the source wiring to outside the contact surface.

Abstract: A lateral high-breakdown-voltage transistor comprises an n−drain region and an n+ source region formed in a p− silicon substrate, separated from each other, a gate electrode formed on a channel, insulated from the substrate, an n+ drain contact region formed in the drain region, drain wiring electrically connected to the drain region via the drain contact region, a p+ substrate contact region formed in contact with the source region, and source wiring electrically connected to the source region and also connected to the semiconductor layer via the substrate contact region. The transistor is characterized in that the substrate contact regions have respective portions made to be in contact with the source wiring, and accordingly laterally extend from inside the contact surface of the source wiring to outside the contact surface.

Abstract: A lateral high-breakdown-voltage transistor comprises an n− drain region and an n+ source region formed in a p− silicon substrate, separated from each other, a gate electrode formed on a channel, insulated from the substrate, an n+ drain contact region formed in the drain region, drain wiring electrically connected to the drain region via the drain contact region, a p+ substrate contact region formed in contact with the source region, and source wiring electrically connected to the source region and also connected to the semiconductor layer via the substrate contact region. The transistor is characterized in that the substrate contact regions have respective portions made to be in contact with the source wiring, and accordingly laterally extend from inside the contact surface of the source wiring to outside the contact surface.

Abstract: A lateral high-breakdown-voltage transistor comprises an n− drain region and an n+ source region formed in a p− silicon substrate, separated from each other, a gate electrode formed on a channel, insulated from the substrate, an n+ drain contact region formed in the drain region, drain wiring electrically connected to the drain region via the drain contact region, a p+ substrate contact region formed in contact with the source region, and source wiring electrically connected to the source region and also connected to the semiconductor layer via the substrate contact region. The transistor is characterized in that the substrate contact regions have respective portions made to be in contact with the source wiring, and accordingly laterally extend from inside the contact surface of the source wiring to outside the contact surface.

Abstract: A lateral high-breakdown-voltage transistor comprises an n− drain region and an n+ source region formed in a p− silicon substrate, separated from each other, a gate electrode formed on a channel, insulated from the substrate, an n+ drain contact region formed in the drain region, drain wiring electrically connected to the drain region via the drain contact region, a p+ substrate contact region formed in contact with the source region, and source wiring electrically connected to the source region and also connected to the semiconductor layer via the substrate contact region. The transistor is characterized in that the substrate contact regions have respective portions made to be in contact with the source wiring, and accordingly laterally extend from inside the contact surface of the source wiring to outside the contact surface.

Abstract: A lateral high-breakdown-voltage transistor comprises an n− drain region and an n+ source region formed in a p− silicon substrate, separated from each other, a gate electrode formed on a channel, insulated from the substrate, an n+ drain contact region formed in the drain region, drain wiring electrically connected to the drain region via the drain contact region, a p+ substrate contact region formed in contact with the source region, and source wiring electrically connected to the source region and also connected to the semiconductor layer via the substrate contact region. The transistor is characterized in that the substrate contact regions have respective portions made to be in contact with the source wiring, and accordingly laterally extend from inside the contact surface of the source wiring to outside the contact surface.

Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

Abstract: A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.

Abstract: A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.

Abstract: A thyristor with an insulated gate includes a p-type emitter layer, an n-type base layer, a p-type base layer, and an n-type emitter layer. A drain electrode contacting the p-type base layer is formed adjacent to one side of the n-type emitter layer. An n-type drain layer, which is short-circuited with the p-type base layer by the drain electrode, is formed. An n-type source layer is formed a predetermined distance away from the n-type drain layer. A turn-off insulated gate is formed between the n-type source layer and the n-type drain layer. A source electrode is connected to a cathode electrode. Thereby, turn-off capability of the thyristor can be improved.

Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

Abstract: There is disclosed a single-gate type conductivity-modulation field effect transistor having a semiconductive substrate, a base layer, and a source layer formed in the base layer. A source electrode is provided on a surface of the substrate, for electrically shorting the base layer with the source layer. A drain layer is provided in the substrate surface. A drain electrode is formed on the substrate surface to be in contact with the drain layer. A gate electrode is insulatively provided above the substrate surface, for covering a certain surface portion of the base layer which is positioned between the substrate and the source layer to define a channel region below the gate electrode. A lightly doped semiconductor diffusion layer is formed in the substrate surface so as to overlap said base layer and said drain layer. The diffusion layer having an impurity density which is varied continuously through the thickness of the diffusion layer.

Abstract: A semiconductor device including a semiconductive substrate having first and second opposite surfaces; a thyristor formed on the substrate and including a base layer formed in the first surface of the substrate, a first emitter layer formed in the base layer, a conductive layer electrically connected to the emitter layer to serve as a cathode electrode, a first gate electrode connected to the base layer, a second emitter layer formed in the second surface of the substrate, a drain layer formed in the second emitter layer, a conductive layer for electrically connecting the second emitter layer with said drain layer and for serving as an anode electrode of said thyristor. A metal oxide semiconductor field effect transistor is provided to accelerate the flow of carriers in said thyristor to the anode electrode to turn off said thyristor.

Abstract: A conductivity-modulation MOSFET employs a substrate of an N type conductivity as its N base. A first source layer of a heavily-doped N type conductivity is formed in a P base layer formed in the N base. A source electrode electrically conducts the P base and the source. A first gate electrode insulatively covers a channel region defined by the N.sup.+ source layer in the P base. A P drain layer is formed on an opposite substrate surface. An N.sup.+ second source layer is formed in a P type drain layer by diffusion to define a second channel region. A second gate electrode insulatively covers the second channel region, thus providing a voltage-controlled turn-off controlling transistor. A drain electrode of the MOSFET conducts the P type drain and second source.

Abstract: There is disclosed a single-gate type conductivity-modulation field effect transistor having a first base layer, a second base layer, and a source layer formed in the second base layer. A source electrode is provided on a surface of the first base layer, for electrically shorting the second base layer with the source layer. A drain layer is provided in the first base layer surface. A drain electrode is formed on the layer surface to be in contact with the drain layer. A gate electrode is insulatively provided above the layer surface, for covering a certain surface portion of the second base layer which is positioned between the first base layer and the source layer to define a channel region below the gate electrode. A heavily-doped semiconductor layer is formed in the drain layer to have the opposite conductivity type to that of the drain layer. This semiconductor layer is in contact with the drain electrode.