Abstract: A display device according to an aspect of the present invention includes a cover member and a display panel. The cover member includes a base material and a light-shielding layer provided in a frame-like manner. A double-faced adhesive sheet is provided so as to cover the surface of the base material and an edge portion on an inner circumferential side of the light-shielding layer. A plurality of grooves not deep enough to penetrate the light-shielding layer are provided on the edge portion on the inner circumferential side of the light-shielding layer to which the double-faced adhesive sheet is bonded. The grooves extend from the inner circumference toward an outer circumference of the light-shielding layer. The grooves are arranged side by side along the inner circumference of the light-shielding layer.

Abstract: A display device according to an aspect of the present invention includes a cover member and a display panel. The cover member includes a base material and a light-shielding layer provided in a frame-like manner. A double-faced adhesive sheet is provided so as to cover the surface of the base material and an edge portion on an inner circumferential side of the light-shielding layer. A plurality of grooves not deep enough to penetrate the light-shielding layer are provided on the edge portion on the inner circumferential side of the light-shielding layer to which the double-faced adhesive sheet is bonded. The grooves extend from the inner circumference toward an outer circumference of the light-shielding layer. The grooves are arranged side by side along the inner circumference of the light-shielding layer.

Abstract: A flat display device has a circuit configuration in which a division-driving system and an aspect conversion are integrated with each other, and performs driving appropriate to achieve higher resolution even in driving a display unit. The device comprises a memory circuit which includes n unit memories each storing unit data, a display unit of which the horizontal driver is supplied signals read from the memory circuit and of which the regions divided into a plurality of portions in a horizontal direction is division-driven, and a memory control circuit which divides a digital video signal of one line into n, supplies n pieces of the unit data to the n unit memories, selects each direction of write or read addresses of the n unit memories, and outputs the read addresses so that the arrangement order of the unit data for the adjacent regions is set in an inversion horizontal direction.

Abstract: According to an embodiment of the invention, even if a sample-and-hold circuit samples a signal from a signal processor to a display unit, an image quality reduction is hard to occur. According to an embodiment of the invention, there is provided a flat-panel display device includes a phase control circuit setting a state that a first parallel arrangement RGB pixel signal shifts by 120 degrees, a sample-and-hold circuit sampling a second parallel arrangement RGB pixel signal parallel-output from the phase control circuit to obtain a series arrangement RGB pixel signal, which is three times as much as a single pixel signal, and a driver supplying the series arrangement RGB pixel signal to the corresponding display pixel.

Abstract: According to one embodiment of the present invention, a flat display device which makes drive voltage polarity of pixels of adjacent lines reversed polarity, while drives to reverse drive voltage polarity of the same line on a frame-by-frame basis, has common voltage generation circuit for supplying a common voltage signal to a facing electrode of the flat display device and a control circuit for generating a common voltage control signal supplied to the common voltage generation circuit. The control circuit obtains a control signal for generating common voltage whose average DC potential does not vary, by using a horizontal synchronization timing signal, a vertical synchronization timing signal, and a clock signal. In order to obtain the control signal, the device has an (fh/2) signal generation circuit, an (fv/2) signal generation circuit, an (fh×n) signal generation circuit, an multiplication circuit, a selection control circuit, and a selection circuit.

Abstract: There is disclosed a flat display unit which can obtain color signals adapted to a pixel arrangement. The unit has a gate drive circuit and a source drive circuit. Among R, G, B input video signals, a G signal is regarded as a color signal of a reference, R and B signals are regarded as second and third color signals, a plurality of samples of the R signal are multiplied by coefficients and synthesized to generate a first interpolation color signal R?, a plurality of samples of the B signal are multiplied by coefficients and synthesized to generate a second interpolation color signal B?. The R?, B? and G signal are successively selected and supplied to the source drive circuit.

Abstract: According to an embodiment of the invention, even if a sample-and-hold circuit samples a signal from a signal processor to a display unit, an image quality reduction is hard to occur. According to an embodiment of the invention, there is provided a flat-panel display device includes a phase control circuit setting a state that a first parallel arrangement RGB pixel signal shifts by 120 degrees, a sample-and-hold circuit sampling a second parallel arrangement RGB pixel signal parallel-output from the phase control circuit to obtain a series arrangement RGB pixel signal, which is three times as much as a single pixel signal, and a driver supplying the series arrangement RGB pixel signal to the corresponding display pixel.

Abstract: A flat display device includes, vertical synchronization lock means which generates an internal vertical synchronization signal, a window signal generating circuit which generates a window signal by use of the internal vertical synchronization signal, a detecting circuit which detects whether or not an external vertical synchronization signal is present in a period of the window signal, and a determination circuit which determines whether a preset condition that a plurality of detection signals are present in a preset period is satisfied or not and controls an output inhibition circuit to inhibit a gate signal from being output when the preset condition is not satisfied.

Abstract: A flat display device has a circuit configuration in which a division-driving system and an aspect conversion are integrated with each other, and performs driving appropriate to achieve higher resolution even in driving a display unit. The device comprises a memory circuit which includes n unit memories each storing unit data, a display unit of which the horizontal driver is supplied signals read from the memory circuit and of which the regions divided into a plurality of portions in a horizontal direction is division-driven, and a memory control circuit which divides a digital video signal of one line into n, supplies n pieces of the unit data to the n unit memories, selects each direction of write or read addresses of the n unit memories, and outputs the read addresses so that the arrangement order of the unit data for the adjacent regions is set in an inversion horizontal direction.

Abstract: According to one embodiment of the present invention, a flat display device which makes drive voltage polarity of pixels of adjacent lines reversed polarity, while drives to reverse drive voltage polarity of the same line on a frame-by-frame basis, has common voltage generation circuit for supplying a common voltage signal to a facing electrode of the flat display device and a control circuit for generating a common voltage control signal supplied to the common voltage generation circuit. The control circuit obtains a control signal for generating common voltage whose average DC potential does not vary, by using a horizontal synchronization timing signal, a vertical synchronization timing signal, and a clock signal. In order to obtain the control signal, the device has an (fh/2) signal generation circuit, an (fv/2) signal generation circuit, an (fh×n) signal generation circuit, an multiplication circuit, a selection control circuit, and a selection circuit.

Abstract: A flat display device includes, vertical synchronization lock means which generates an internal vertical synchronization signal, a window signal generating circuit which generates a window signal by use of the internal vertical synchronization signal, a detecting circuit which detects whether or not an external vertical synchronization signal is present in a period of the window signal, and a determination circuit which determines whether a preset condition that a plurality of detection signals are present in a preset period is satisfied or not and controls an output inhibition circuit to inhibit a gate signal from being output when the preset condition is not satisfied.

Abstract: There is disclosed a flat display unit which can obtain color signals adapted to a pixel arrangement. The unit has a gate drive circuit and a source drive circuit. Among R, G, B input video signals, a G signal is regarded as a color signal of a reference, R and B signals are regarded as second and third color signals, a plurality of samples of the R signal are multiplied by coefficients and synthesized to generate a first interpolation color signal R?, a plurality of samples of the B signal are multiplied by coefficients and synthesized to generate a second interpolation color signal B?. The R?, B? and G signal are successively selected and supplied to the source drive circuit.

Abstract: There is disclosed a device and method for displaying images on a first area A and a second area B of the display screen of a liquid crystal display device. The first area A has an aspect ratio of 12:9. The second area B has an aspect ratio of 9:4. An image signal is displayed on the first area A, while a remaining area signal is displayed on the second area B. The liquid crystal display device has a control circuit that produces a horizontal clock signal having a frequency of fck3 and a horizontal start signal XST during 0.8H of one horizontal scanning period of 1H. Either image signal VD1 or VD2 corresponding to the first area A having an aspect ratio of 12:9 is sampled. The frequency fck3 satisfies the relation 2×fck3=3×fck1 (where fck1 is the number of pixels on a horizontal line×fh/0.8). The control circuit produces a horizontal clock signal (XCK) having a frequency of fck4 and the horizontal start signal XST during a period shorter than the remaining period of 0.2H.

Abstract: A flat-panel display device changes the level of a video signal supplied from a video signal source in the horizontal blanking period on the basis of a selected voltage value from a voltage generation circuit, and this voltage is sampled in response to a sampling clock from a timing generation circuit and is latched by a signal line driving circuit. The latched signal is supplied to a flat display panel along with a scanning signal from a scanning line driving circuit to display an image according to the aspect ratio of the flat display panel.

Abstract: A liquid crystal display device is composed of a liquid crystal panel including a plurality of pixels and a plurality of data signal lines, and a panel control unit CNT for controlling the liquid crystal panel so that a selected one of a high vision signal image and an NTSC signal image can be displayed. The control unit includes an auxiliary video signal generating circuit for generating an auxiliary video signal representing an auxiliary image to be displayed in first and second remainder areas provided on both sides of a display area for displaying an NTSC signal image on the screen of the liquid crystal panel. The control unit further includes a circuit for driving the data signal lines according to results obtained by sampling the auxiliary video signal in a horizontal blanking period of an NTSC video signal and the NTSC video signal in a period excluding the horizontal blanking period from one horizontal scanning period of the NTSC video signal.

Abstract: A method of displaying an image on a display screen and a image display device are described. The display device includes a display screen, horizontal and vertical scanning circuits, and a control circuit. The display screen has a predetermined aspect ratio of its lateral axis length and its longitudinal axis length. The horizontal scanning circuits derive signal voltages from a video signal in accordance with a clock signal and provide the same to pixels of horizontal pixel lines. The vertical scanning circuits select the horizontal pixel lines. The control circuit includes a divider circuit to divide a reference clock signal by first and second dividing ratios, and a switching circuit to select either a combination of the reference clock signal and an output signal of the divider circuit by the first dividing ratio or an output of the divider circuit divided by the second dividing ratio so that it may supply the clock signal to the horizontal scanning circuit.