Patents by Inventor Kimio Hara

Kimio Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120302061
    Abstract: In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.
    Type: Application
    Filed: August 1, 2012
    Publication date: November 29, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki ARIE, Nobuaki UMEMURA, Nobuyoshi HATTORI, Nobuto NAKANISHI, Kimio HARA, Kyoya NITTA, Makoto ISHIKAWA
  • Patent number: 8242605
    Abstract: In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: August 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Arie, Nobuaki Umemura, Nobuyoshi Hattori, Nobuto Nakanishi, Kimio Hara, Kyoya Nitta, Makoto Ishikawa
  • Publication number: 20100327349
    Abstract: In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 30, 2010
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki ARIE, Nobuaki UMEMURA, Nobuyoshi HATTORI, Nobuto NAKANISHI, Kimio HARA, Kyoya NITTA, Makoto ISHIKAWA