Abstract: One end of a fuse is connected to a ground point via a transistor N1A, and the other end thereof is connected to a node VaA. For example, at a fuse connection case, when INTV=“H” is input to the gate of the transistor N1A, the node VaA becomes “L.” At INTV=“L”, a transistor P1A having a low “on” resistance turns ON, and the node VaA is quickly precharged. At INTV=“H”, the transistor N1A turns ON, and the node VaA is quickly discharged.

Abstract: A memory data protection system is disclosed, which comprises a memory circuit, a protection contents indicating section which stores a security bit and a protection bit, a protection function circuit which determines permission/prohibition of reading of data from the memory circuit and permission/prohibition of writing of data to the memory circuit in accordance with the security bit and the protection bit, and a protection function locking/unlocking circuit which makes the protection function circuit in a lock state to forcibly prohibit reading of data from the memory circuit and writing of data into the memory circuit in a time period from when a power supply is turned on till when the protection function circuit completes reading of the security bit and the protection bit from the protection contents indicating section into data buses, and after lapse of the time period, the protection function locking/unlocking circuit unlocks the lock state.

Abstract: A redundancy fuse circuit including a function of replacing a defective cell in a memory cell array with a redundancy cell, comprising a fuse circuit in which an address of the defective cell or a block including the defective cell is programmed as a defective address by presence/absence of cut-off of a fuse, a data latch circuit which latches a signal supplied from a tester to program the defective address in a dummy manner, and a comparator which replaces the defective cell with the redundancy cell based on an address signal supplied from the tester and an output signal of the data latch circuit at an operation confirmation time of the redundancy fuse circuit.

Abstract: A redundancy fuse circuit including a function of replacing a defective cell in a memory cell array with a redundancy cell, comprising a fuse circuit in which an address of the defective cell or a block including the defective cell is programmed as a defective address by presence/absence of cut-off of a fuse, a data latch circuit which latches a signal supplied from a tester to program the defective address in a dummy manner, and a comparator which replaces the defective cell with the redundancy cell based on an address signal supplied from the tester and an output signal of the data latch circuit at an operation confirmation time of the redundancy fuse circuit.

Abstract: One end of a fuse is connected to a ground point via a transistor N1A, and the other end thereof is connected to a node VaA. For example, at a fuse connection case, when INTV=“H” is input to the gate of the transistor N1A, the node VaA becomes “L.” At INTV=“L”, a transistor P1A having a low “on” resistance turns ON, and the node VaA is quickly precharged. At INTV=“H”, the transistor N1A turns ON, and the node VaA is quickly discharged.

Abstract: A memory data protection system is disclosed, which comprises a memory circuit, a protection contents indicating section which stores a security bit and a protection bit, a protection function circuit which determines permission/prohibition of reading of data from the memory circuit and permission/prohibition of writing of data to the memory circuit in accordance with the security bit and the protection bit, and a protection function locking/unlocking circuit which makes the protection function circuit in a lock state to forcibly prohibit reading of data from the memory circuit and writing of data into the memory circuit in a time period from when a power supply is turned on till when the protection function circuit completes reading of the security bit and the protection bit from the protection contents indicating section into data buses, and after lapse of the time period, the protection function locking/unlocking circuit unlocks the lock state.

Abstract: A semiconductor memory device includes a memory cell array, a read control circuit, a row decoder, a column decoder, a sense amplifier, and a sense amplifier control circuit. The read control circuit produces a precharge signal to precharge a bit line of the memory cell array. The sense amplifier amplifies data read onto the bit line. In reading data from a memory cell, the sense amplifier control circuit enables the sense amplifier and inhibits entry of read data from a memory cell into the sense amplifier only for a fixed interval after a fixed time after the precharging signal has been negated. The sense amplifier control circuit allows entry of read data into the sense amplifier while the sense amplifier is being disabled.

Abstract: A semiconductor memory device includes a memory cell array, a read control circuit, a row decoder, a column decoder, a sense amplifier, and a sense amplifier control circuit. The read control circuit produces a precharge signal to precharge a bit line of the memory cell array. The sense amplifier amplifies data read onto the bit line. In reading data from a memory cell, the sense amplifier control circuit enables the sense amplifier and inhibits entry of read data from a memory cell into the sense amplifier only for a fixed interval after a fixed time after the precharging signal has been negated. The sense amplifier control circuit allows entry of read data into the sense amplifier while the sense amplifier is being disabled.

Abstract: A chopper type voltage comparison circuit is disclosed which restrain leakage current between an input and output nodes of each amplifying circuit to enable normal voltage comparisons even if a threshold voltage for each transistor is reduced to diminish a power supply voltage.

Abstract: A method and apparatus for cutting a continuous corrugated member while conveying it in a longitudinal direction thereof, in which a movable cutter blade is moved forward in the same direction as the conveying direction of the corrugated member at the same speed as the conveying speed of the corrugated member. The cutter blade is also reciprocated to cut the corrugated member when the cutter blade is moved forward.