Patents by Inventor Kimio Ooe

Kimio Ooe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5249276
    Abstract: An address translation apparatus which includes a memory for storing a plurality of physical addresses, and a content addressable memory unit which stores a plurality of signal pairs that correspond to the plurality of physical addresses, each of the signal paris includes a logical address that corresponds to one of the plurality of physical addresses and memory protection level data that indicates a memory protection level allocated to a memory position of the one of the physical addresses. The content addressable memory unit includes apparatus for searching a signal pair that has a logical address in coincident with a logical address being subjected to address translation and comparing memory protection level data to comparative data at a bit position which is indicated to be the bit position to be searched by mask data, in response to the logical address translation.
    Type: Grant
    Filed: June 20, 1988
    Date of Patent: September 28, 1993
    Assignees: Hitachi, Ltd., Hitachi Micro Computer Engineering Ltd.
    Inventors: Tetsuro Honmura, Katsuaki Takagi, Shunpei Kawasaki, Nobutaka Amano, Kimio Ooe
  • Patent number: 4891773
    Abstract: In a logic simulation method for performing logic simulation of a logic circuit including a circuit with unknown internal logic, the circuit itself with the unknown internal logic is used. The internal status of the circuit is set at an objective status using the interrupt operation afforded by the circuit and thereafter, input signal value is applied to the circuit to obtain a resultant output. For other logic circuits without unknown internal logic, software logic simulation is performed. During such software logic simulation, the actual circuit with unknown internal logic is called.
    Type: Grant
    Filed: April 24, 1987
    Date of Patent: January 2, 1990
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Kimio Ooe, Nobutaka Amano, Takashige Kubo, Kaoru Moriwaki