Abstract: An apparatus for controlling the transfer of data comprises registers for setting an address of a memory and data to be stored in the memory at the address, and a control unit for controlling the registers to set the address and data. In a case where an immediate data transfer command is produced, a physical address is defined by including the immediate data transfer command partly therein. The physical address thus defined is automatically set in the register for setting an address of a memory without receiving an address setting command so that the data stored in the register for setting data are written into the memory at the physical address.

Abstract: In an apparatus for controlling a signal processing system to operate in high and low speed modes, a control unit determines a speed of system clock signals in accordance with the interpretation of a program when external clock signals are received. When a speed of the system clock signals is determined, the control unit controls the production of the system clock signals of a frequency dependent on the speed. As a result, a peripheral circuit of a low speed can be controlled to operate without the necessity of a complicated interface circuit, and a system of a high speed such as a system for the so-called television game can also be controlled to operate. Further, a limitation on an operation speed of a peripheral circuit is excluded so that an expansion of a signal processing system can be easy to be performed. Still further, all circuits of the signal processing system can be under operation states because a low speed mode is first realized when a power supply is turned on.

Abstract: A video signal processor comprising: a device defining a color pallet for converting a color code specifying the color of each pixel of a display picture into digital RGB color data; and a conversion system for converting the RGB color data into a luminance signal and two color-difference signals represented by analog values, wherein the conversion system includes: a memory storing digital values constituting a conversion system for converting the digital RGB color data into a luminance signal and two color-difference signals represented by digital values; and a digital-analog converter connected to the conversion system for converting the luminance signal and two color-difference signals represented by digital values into the luminance signal and two color-difference signals represented by analog values.

Abstract: An apparatus for controlling the access of a video memory comprises a group of registers in which various kinds of control data are set to access a video memory. The group of the registers are set to store data for detecting scanning rasters, incrementing or decrementing an address of the video memory which is accessed, and starting a DMA transfer of image data. Therefore, various kinds of accessing modes can be performed without the necessity of a complicated software.

Abstract: An apparatus for controlling the transfer of data comprises registers for setting an address of a memory and data to be stored in the memory at the address, and a control unit for controlling the registers to set the address and data. In a case where an immediate data transfer command is produced, a physical address is defined by including the immediate data transfer command partly therein. The physical address thus defined is automatically set in the register for setting an address of a memory without receiving an address setting command so that the data stored in the register for setting data are written into the memory at the physical address.

Abstract: A cathode-ray tube control device displays data obtained from a personal computer on the screen of a television receiver in superimposing relation to the picture of a broadcast. Clock pulses are generated, and these are counted in synchronism with the horizontal and vertical synchronizing signals from the television receiver. Display timing signals including horizontal scanning display period signal, horizontal retrace period signal, vertical scanning display period signal, and vertical retrace period signal are delivered in response to the resultant counts. Then, read-out of data to be displayed is controlled in accordance with the produced timing signals, and the read data is displayed on the screen such that it is superimposed on the picture of a television broadcast. If desired, the frequency of the timing signals may be slightly varied so as to scroll said data across the television picture.

Abstract: In an apparatus for producing video signals in which a memory storing color data is addressed with an address signal determined by video data to produce color data, an analog RGB signal producing circuit in which the color data read from the memory are converted to analog signals is provided so that a color image can be displayed on a CRT or an exclusively used monitor means to which the color data are directly supplied. Further, a signal conversion circuit, a video color signal producing circuit and a composite circuit are provided wherein a luminance signal and color difference signals are produced in accordance with the color data in the signal conversion circuit, and the luminance signal is converted to an analog luminance signal and color carriers are produced by modulating analog signals converted from the color difference signals with the color subcarriers in the video color signal producing circuit.

Abstract: In a central processing unit, there are provided a address register for storing source and destination addresses and a count register for storing a length of a block data transfer. The address and count registers are wholly or partly composed of a wide use register having other functions. Therefore, the number of registers is minimized.

Abstract: An apparatus for the control of an access to a video memory comprises a memory width register having a content of a number of dot periods by which an access timing is determined to address a video memory. Therefore, an access timing is easily controlled dependent on a memory speed of the video memory only by changing the content of the memory width register. When the video memory is accessed during a display cycle of the video memory, video data may be stored in a buffer memory, and transferred from the buffer memory after the display cycle is finished.

Abstract: In an apparatus for controlling the access of a memory, a memory is accessed in accordance with a physical address composed of a predetermined number of bits larger than another predetermined number of which a logical address is composed. For the purpose, a logical address region is equally divided by the number of mapping registers from which one register is selected in accordance with a content of a logical address. A physical address region is divided to provide a plurality of blocks from which one block is selected in accordance with a content of the selected one register.

Abstract: Apparatus for displaying a sprite on a screen comprises sprite attribute tables each including coordinates indicating a display position of a sprite, a pattern code defining the sprite in regard to pattern data, and control data defining a display mode of the sprite. A sprite generator is addressed in accordance with the pattern code to supply the pattern data of a sprite to a pattern data buffer. The sprite is displayed in accordance with the coordinates thereof on the screen. Therefore, the sprite is moved on the screen only by changing the coordinates of a corresponding sprite attribute table.

Abstract: In an apparatus for generating sound, there are provided a plurality of channels for generating sounds. Each of the channels includes a memory for storing waveform data, and at least one of the channels includes a noise generator so that various kinds of sounds including rhythm sound-effects sound, effects sound-vibrato etc. are generated. There is further provided a controller by which voice sound signal is passed through the channels so that artificial sound, voice sound etc. are generated. There is still further provided a circuit for adjusting an amplitude level of a whole sound which is obtained by mixing output sounds of the channels so that far and near sound is produced. Further, each of the channels includes left and right attenuators which divide a channel sound into left and right channel sounds.

Abstract: A cathode-ray tube control device displays data obtained from a personal computer on the screen of a television receiver in superimposing relation to the picture of a broadcast. Clock pulses are generated, and these are counted in synchronism with the horizontal and vertical synchronizing signals from the television receiver. Display timing signals including horizontal scanning display period signal, horizontal retrace period signal, vertical scanning display period signal, and vertical retrace period signal are delivered in response to the resultant counts. Then, read-out of data to be displayed is controlled in accordance with the produced timing signals, and the read data is displayed on the screen such that it is superimposed on the picture of a television broadcast. If desired, the frequency of the timing signals may be slightly varied so as to scroll said data across the television picture.