Patents by Inventor Kimitaka Endo
Kimitaka Endo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10032646Abstract: An interconnect element 130 can include a dielectric layer 116 having a top face 116b and a bottom face 116a remote from the top face, a first metal layer defining a plane extending along the bottom face and a second metal layer extending along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces 132, 134. A plurality of conductive protrusions 112 can extend upwardly from the plane defined by the first metal layer 102 through the dielectric layer 116. The conductive protrusions 112 can have top surfaces 126 at a first height 115 above the first metal layer 132 which may be more than 50% of a height of the dielectric layer. A plurality of conductive vias 128 can extend from the top surfaces 126 of the protrusions 112 to connect the protrusions 112 with the second metal layer.Type: GrantFiled: September 30, 2016Date of Patent: July 24, 2018Assignee: Tessera, Inc.Inventors: Belgacem Haba, Vage Oganesian, Kimitaka Endo
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Patent number: 9856135Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.Type: GrantFiled: December 15, 2016Date of Patent: January 2, 2018Assignee: Invensas CorporationInventors: Chang Myung Ryu, Kimitaka Endo, Belgacem Haba, Yoichi Kubota
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Publication number: 20170096329Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.Type: ApplicationFiled: December 15, 2016Publication date: April 6, 2017Inventors: Chang Myung Ryu, Kimitaka Endo, Belgacem Haba, Yoichi Kubota
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Publication number: 20170018440Abstract: An interconnect element 130 can include a dielectric layer 116 having a top face 116b and a bottom face 116a remote from the top face, a first metal layer defining a plane extending along the bottom face and a second metal layer extending along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces 132, 134. A plurality of conductive protrusions 112 can extend upwardly from the plane defined by the first metal layer 102 through the dielectric layer 116. The conductive protrusions 112 can have top surfaces 126 at a first height 115 above the first metal layer 132 which may be more than 50% of a height of the dielectric layer. A plurality of conductive vias 128 can extend from the top surfaces 126 of the protrusions 112 to connect the protrusions 112 with the second metal layer.Type: ApplicationFiled: September 30, 2016Publication date: January 19, 2017Inventors: Belgacem Haba, Vage Oganesian, Kimitaka Endo
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Patent number: 9524947Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.Type: GrantFiled: December 1, 2014Date of Patent: December 20, 2016Assignee: Invensas CorporationInventors: Chang Myung Ryu, Kimitaka Endo, Belgacem Haba, Yoichi Kubota
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Patent number: 9282640Abstract: An interconnection element is provided for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon. The interconnection element includes a dielectric element having a major surface. A plated metal layer including a plurality of exposed metal posts can project outwardly beyond the major surface of the dielectric element. Some of the metal posts can be electrically insulated from each other by the dielectric element. The interconnection element typically includes a plurality of terminals in conductive communication with the metal posts. The terminals can be connected through the dielectric element to the metal posts. The posts may be defined by plating a metal onto exposed co-planar surfaces of a mandrel and interior surfaces of openings in a mandrel, after which the mandrel can be removed.Type: GrantFiled: June 27, 2013Date of Patent: March 8, 2016Assignee: Tessera, Inc.Inventors: Jinsu Kwon, Kimitaka Endo, Sean P. Moran
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Publication number: 20150087146Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.Type: ApplicationFiled: December 1, 2014Publication date: March 26, 2015Inventors: Chang Myung Ryu, Kimitaka Endo, Belgacem Haba, Yoichi Kubota
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Patent number: 8900464Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.Type: GrantFiled: June 10, 2013Date of Patent: December 2, 2014Assignee: Invensas CorporationInventors: Chang Myung Ryu, Kimitaka Endo, Belgacem Haba, Yoichi Kubota
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Patent number: 8859420Abstract: A method of fabricating an interconnect element may include fabricating a metal layer that overlies a carrier layer and that includes a plurality of metal traces; providing a dielectric element to overlie the metal layer and the carrier layer; providing a plurality of metal posts; and removing the carrier layer to expose the first major surface of the dielectric element and the outer surfaces of the plurality of metal traces.Type: GrantFiled: April 12, 2011Date of Patent: October 14, 2014Assignee: Invensas CorporationInventors: Kimitaka Endo, Norihito Masuda, Tomokazu Shimada
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Publication number: 20130341299Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.Type: ApplicationFiled: June 10, 2013Publication date: December 26, 2013Inventors: Chang Myung RYU, Kimitaka ENDO, Belgacem HABA, Yoichi KUBOTA
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Publication number: 20130286619Abstract: An interconnection element is provided for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon. The interconnection element includes a dielectric element having a major surface. A plated metal layer including a plurality of exposed metal posts can project outwardly beyond the major surface of the dielectric element. Some of the metal posts can be electrically insulated from each other by the dielectric element. The interconnection element typically includes a plurality of terminals in conductive communication with the metal posts. The terminals can be connected through the dielectric element to the metal posts. The posts may be defined by plating a metal onto exposed co-planar surfaces of a mandrel and interior surfaces of openings in a mandrel, after which the mandrel can be removed.Type: ApplicationFiled: June 27, 2013Publication date: October 31, 2013Inventors: Jinsu Kwon, Kimitaka Endo, Sean P. Moran
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Patent number: 8505199Abstract: An interconnection element is provided for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon. The interconnection element includes a dielectric element having a major surface. A plated metal layer including a plurality of exposed metal posts can project outwardly beyond the major surface of the dielectric element. Some of the metal posts can be electrically insulated from each other by the dielectric element. The interconnection element typically includes a plurality of terminals in conductive communication with the metal posts. The terminals can be connected through the dielectric element to the metal posts. The posts may be defined by plating a metal onto exposed co-planar surfaces of a mandrel and interior surfaces of openings in a mandrel, after which the mandrel can be removed.Type: GrantFiled: August 15, 2008Date of Patent: August 13, 2013Assignee: Tessera, Inc.Inventors: Jinsu Kwon, Kimitaka Endo, Sean Moran
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Patent number: 8461460Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.Type: GrantFiled: July 8, 2009Date of Patent: June 11, 2013Assignee: Invensas CorporationInventors: Chang Myung Ryu, Kimitaka Endo, Belgacem Haba, Yoichi Kubota
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Patent number: 8299368Abstract: An interconnection element and method for making same is disclosed. The interconnection element may include a plurality of metal conductors, a plurality of solid metal bumps and a low melting point (LMP) metal layer. The solid metal bumps overly and project in a first direction away from respective ones of the conductors. Each bump has at least one edge bounding the bump in at least a second direction transverse to the first direction. The low melting point (LMP) metal layer has a first face joined to the respective ones of the conductors and bounded in the second direction by at least one edge and a second face joined to the bumps. The edges of the bumps and the LMP layer are aligned in the first direction, and the LMP metal layer has a melting temperature substantially lower than the conductors.Type: GrantFiled: December 23, 2008Date of Patent: October 30, 2012Assignee: Invensas CorporationInventor: Kimitaka Endo
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Patent number: 8119516Abstract: A method for forming a bump structure and a bump structure for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon, used as an electric connection in an electronic circuit, includes the steps of forming a mandrel by steps including forming at least one opening extending through a bump-forming die body in the thickness direction thereof and positioning a bump-forming die lid on a surface of the bump-forming die body so as to cover one end of the opening and to thereby define a bump-forming recess. The bump-forming die body may be comprised of a metal sheet. A metal layer is formed at least on an inner surface of the bump-forming die lid exposed within the bump-forming recess. The mandrel is removed so as to expose the metal layer and form a bump structure.Type: GrantFiled: November 4, 2008Date of Patent: February 21, 2012Assignee: Tessera Interconnect Materials, Inc.Inventor: Kimitaka Endo
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Publication number: 20110252637Abstract: A method of fabricating an interconnect element may include fabricating a metal layer that overlies a carrier layer and that includes a plurality of metal traces; providing a dielectric element to overlie the metal layer and the carrier layer; providing a plurality of metal posts; and removing the carrier layer to expose the first major surface of the dielectric element and the outer surfaces of the plurality of metal traces.Type: ApplicationFiled: April 12, 2011Publication date: October 20, 2011Applicant: TESSERA INTERCONNECT MATERIALS, INC.Inventors: Kimitaka Endo, Norihito Masuda, Tomokazu Shimada
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Patent number: 7923828Abstract: An interconnect element is provided which includes a dielectric element having a first major surface, a second major surface remote from the first major surface, and a plurality of recesses extending inwardly from the first major surface. A plurality of metal traces are embedded in the plurality of recesses, the metal traces having outer surfaces substantially co-planar with the first major surface and inner surfaces remote from the outer surfaces. A plurality of posts extend from the inner surfaces of the plurality of metal traces through the dielectric element, the plurality of posts having tops exposed at the second major surface. A multilayer wiring board including a plurality of such interconnect elements is also provided, as well as various methods for making such interconnect elements and multilayer wiring boards.Type: GrantFiled: September 30, 2005Date of Patent: April 12, 2011Assignee: Tessera Interconnect Materials, Inc.Inventors: Kimitaka Endo, Norihito Masuda, Tomokazu Shimada
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Publication number: 20100242270Abstract: A manufacturing method for a wiring circuit board includes the steps of: forming a board on a surface of a metal layer directly or indirectly through an etching barrier layer; forming an insulating film on the surface of the metal layer; polishing the insulating film to an extent to which a top face of the bump is exposed; and forming a solder ball on the top face of the bump.Type: ApplicationFiled: February 16, 2010Publication date: September 30, 2010Inventors: Tomoo Iijima, Kimitaka Endo, Kazuo Ikenaga, Hiroshi Odaira, Naoto Minari, Takashi Kato
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Publication number: 20100071944Abstract: A multiple wiring layer interconnection element includes capacitors or other electrical components embedded between a first exposed wiring layer and a second exposed wiring layer of the interconnection element. Internal wiring layers and are provided between exposed surfaces of the respective capacitors, the internal wiring layers being electrically insulated from the capacitors by dielectric layers. The internal wiring layers are isolated from each other by an internal dielectric layer. Conductive vias provide conductive interconnection between the two internal wiring layers. A method of fabricating a multiple wiring layer interconnection element is also provided.Type: ApplicationFiled: December 17, 2007Publication date: March 25, 2010Applicant: TESSERA INTERCONNECT MATERIALS, INC.Inventor: Kimitaka Endo
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Publication number: 20100044860Abstract: An interconnection element can include a substrate, e.g., a connection substrate, element of a package, circuit panel or microelectronic substrate, e.g., semiconductor chip, the substrate having a plurality of metal conductive elements such as conductive pads, contacts, bond pads, traces, or the like exposed at the surface. A plurality of solid metal posts may overlie and project away from respective ones of the conductive elements. An intermetallic layer can be disposed between the posts and the conductive elements, such layer providing electrically conductive interconnection between the posts and the conductive elements. Bases of the posts adjacent to the intermetallic layer can be aligned with the intermetallic layer.Type: ApplicationFiled: July 30, 2009Publication date: February 25, 2010Applicant: Tessera Interconnect Materials, Inc.Inventors: Belgacem Haba, Chang Myung Ryu, Kimitaka Endo, Christopher Paul Wade