Patents by Inventor Kimitaka Shibata

Kimitaka Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9263853
    Abstract: An optical semiconductor device includes: a resonator end face; an optical waveguide; a window structure located between the resonator end face and the optical waveguide; and a vernier on the window structure and allowing measurement of length of the window structure along an optical axis direction.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: February 16, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yusuke Azuma, Eitaro Ishimura, Kimitaka Shibata
  • Publication number: 20150101161
    Abstract: An optical semiconductor device includes: a resonator end face; an optical waveguide; a window structure located between the resonator end face and the optical waveguide; and a vernier on the window structure and allowing measurement of length of the window structure along an optical axis direction.
    Type: Application
    Filed: June 10, 2014
    Publication date: April 16, 2015
    Inventors: Yusuke Azuma, Eitaro Ishimura, Kimitaka Shibata
  • Patent number: 8841143
    Abstract: A method for manufacturing an optical modulator having a laser diode section and an EAM section. LD growth layers which are semiconductor layers for manufacturing the laser diode section, are formed on a semiconductor substrate. An EAM absorption layer for forming the EAM section is then formed on the semiconductor substrate. The photoluminescent wavelength of the EAM absorption layer is then measured. The LD growth layers are then etched to form a stripe structure section. The width of the stripe structure section is determined such that the difference between the lasing wavelength of the LD section and the photoluminescent wavelength of the EAM section is close to a design value.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: September 23, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kimitaka Shibata
  • Publication number: 20140087493
    Abstract: A method for manufacturing an optical modulator having a laser diode section and an EAM section. LD growth layers which are semiconductor layers for manufacturing the laser diode section, are formed on a semiconductor substrate. An EAM absorption layer for forming the EAM section is then formed on the semiconductor substrate. The photoluminescent wavelength of the EAM absorption layer is then measured. The LD growth layers are then etched to form a stripe structure section. The width of the stripe structure section is determined such that the difference between the lasing wavelength of the LD section and the photoluminescent wavelength of the EAM section is close to a design value.
    Type: Application
    Filed: March 18, 2013
    Publication date: March 27, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventor: Kimitaka Shibata
  • Patent number: 7289546
    Abstract: An n-type first cladding layer, a first guide layer, a first enhancing layer, an active layer, a second enhancing layer, a second guide layer, and a p-type second cladding layer are sequentially stacked on an n-type GaAs substrate. The thickness of each of the first guide layer and the second guide layer is 100 nm or more. In such a semiconductor laser, the difference between the Eg (band gap energy) of the first guide layer and the Eg of the active layer (or the difference between the Eg of the second guide layer and the Eg of the active layer) is made 0.66 times or less of the difference between the Eg of the first cladding layer and the Eg of the active layer (or the difference between the Eg of the second cladding layer and the Eg of the active layer).
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: October 30, 2007
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kimio Shigihara, Yoshihiko Hanamaki, Kimitaka Shibata, Kazushige Kawasaki
  • Patent number: 7259406
    Abstract: A semiconductor optical element having a includes an n-type GaAs buffer layer, an n-type AlGaInP cladding layer, a first InGaAsP (including zero As content)guide layer without added dopant impurities, an InGaAsP (including zero In content) active layer, a second InGaAsP (including zero As content)guide layer without added dopant impurities, a p-type AlGaInP cladding layer, a p-type band discontinuity reduction layer, and a p-type GaAs contact layer sequentially laminated on an n-type GaAs substrate C or Mg is the dopant impurity in the p-type GaAs contact layer, the p-type band discontinuity reduction layer, and the p-type AlGaInP cladding layer.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: August 21, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiko Hanamaki, Kenichi Ono, Kimio Shigihara, Kazushige Kawasaki, Kimitaka Shibata, Naoyuki Shimada
  • Publication number: 20070171948
    Abstract: An n-type first cladding layer, a first guide layer, a first enhancing layer, an active layer, a second enhancing layer, a second guide layer, and a p-type second cladding layer are sequentially stacked on an n-type GaAs substrate. The thickness of each of the first guide layer and the second guide layer is 100 nm or more. In such a semiconductor laser, the difference between the Eg (and gap energy) of the first guide layer and the Eg of the active layer (or the difference between the Eg of the second guide layer and the Eg of the active layer) is made 0.66 times or less of the difference between the Eg of the first cladding layer and the Eg of the active layer (or the difference between the Eg of the second cladding layer and the Eg of the active layer).
    Type: Application
    Filed: October 19, 2006
    Publication date: July 26, 2007
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kimio Shigihara, Yoshihiko Hanamaki, Kimitaka Shibata, Kazushige Kawasaki
  • Publication number: 20060220037
    Abstract: A semiconductor optical element having a includes an n-type GaAs buffer layer, an n-type AlGaInP cladding layer, a first InGaAsP (including zero As content) guide layer without added dopant impurities, an InGaAsP (including zero In content) active layer, a second InGaAsP (including zero As content) guide layer without added dopant impurities, a p-type AlGaInP cladding layer, a p-type band discontinuity reduction layer, and a p-type GaAs contact layer sequentially laminated on an n-type GaAs substrate C or Mg is the dopant impurity in the p-type-GaAs contact layer, the p-type band discontinuity reduction layer, and the p-type AlGaInP cladding layer.
    Type: Application
    Filed: November 2, 2005
    Publication date: October 5, 2006
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiko Hanamaki, Kenichi Ono, Kimio Shigihara, Kazushige Kawasaki, Kimitaka Shibata, Naoyuki Shimada
  • Publication number: 20050286592
    Abstract: A semiconductor laser array device for outputting a higher power includes: a plurality of semiconductor laser chips, arranged in a predetermined pitch; a submount for mounting each semiconductor laser chip; and a heat sink for dissipating heat from the semiconductor laser chip through the submount; wherein a distance S between the centers of the chips and a thickness T of the submount satisfy the following inequality: 2×T?S?10×T, whereby improving efficiency of heat dissipation with a good process yield.
    Type: Application
    Filed: March 14, 2005
    Publication date: December 29, 2005
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Naoyuki Shimada, Kimio Shigihara, Kazushige Kawasaki, Kimitaka Shibata, Tetsuya Yagi, Kenichi Ono, Hideki Haneda
  • Patent number: 5805629
    Abstract: A semiconductor device includes a p type InP substrate with a (001) surface; a mesa structure formed by dry etching, extending along a <110> direction, including semiconductor layers, having (110) side surfaces, and a height H.sub.m ; and mesa burying layers including a p type InP burying layer on the (110) side surfaces and the (001) surface, the p type InP burying layer having a thickness D.sub.p, and an n type InP burying layer on the p type InP burying layer. An angle between a (111)B surface and (001) surface is .theta..sub.111, the growth rates on the (110) side surfaces and on the (001) surface are respectively R.sub.g (110) and R.sub.g (001), an angle .theta. is tan .theta.=R.sub.g (110)/R.sub.g (001) and the critical thickness D.sub.n of the n type InP burying layer on the (001) surface when the n type InP burying layer is not grown on the (111)B surface is ##EQU1## The n type InP burying layer has a thickness D.ltoreq.D.sub.n.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: September 8, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masayoshi Takemi, Tatsuya Kimura, Daisuke Suzuki, Tetsuo Shiba, Kimitaka Shibata