Patents by Inventor Kimitaka Shibata
Kimitaka Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9263853Abstract: An optical semiconductor device includes: a resonator end face; an optical waveguide; a window structure located between the resonator end face and the optical waveguide; and a vernier on the window structure and allowing measurement of length of the window structure along an optical axis direction.Type: GrantFiled: June 10, 2014Date of Patent: February 16, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yusuke Azuma, Eitaro Ishimura, Kimitaka Shibata
-
Publication number: 20150101161Abstract: An optical semiconductor device includes: a resonator end face; an optical waveguide; a window structure located between the resonator end face and the optical waveguide; and a vernier on the window structure and allowing measurement of length of the window structure along an optical axis direction.Type: ApplicationFiled: June 10, 2014Publication date: April 16, 2015Inventors: Yusuke Azuma, Eitaro Ishimura, Kimitaka Shibata
-
Patent number: 8841143Abstract: A method for manufacturing an optical modulator having a laser diode section and an EAM section. LD growth layers which are semiconductor layers for manufacturing the laser diode section, are formed on a semiconductor substrate. An EAM absorption layer for forming the EAM section is then formed on the semiconductor substrate. The photoluminescent wavelength of the EAM absorption layer is then measured. The LD growth layers are then etched to form a stripe structure section. The width of the stripe structure section is determined such that the difference between the lasing wavelength of the LD section and the photoluminescent wavelength of the EAM section is close to a design value.Type: GrantFiled: March 18, 2013Date of Patent: September 23, 2014Assignee: Mitsubishi Electric CorporationInventor: Kimitaka Shibata
-
Publication number: 20140087493Abstract: A method for manufacturing an optical modulator having a laser diode section and an EAM section. LD growth layers which are semiconductor layers for manufacturing the laser diode section, are formed on a semiconductor substrate. An EAM absorption layer for forming the EAM section is then formed on the semiconductor substrate. The photoluminescent wavelength of the EAM absorption layer is then measured. The LD growth layers are then etched to form a stripe structure section. The width of the stripe structure section is determined such that the difference between the lasing wavelength of the LD section and the photoluminescent wavelength of the EAM section is close to a design value.Type: ApplicationFiled: March 18, 2013Publication date: March 27, 2014Applicant: Mitsubishi Electric CorporationInventor: Kimitaka Shibata
-
Patent number: 7289546Abstract: An n-type first cladding layer, a first guide layer, a first enhancing layer, an active layer, a second enhancing layer, a second guide layer, and a p-type second cladding layer are sequentially stacked on an n-type GaAs substrate. The thickness of each of the first guide layer and the second guide layer is 100 nm or more. In such a semiconductor laser, the difference between the Eg (band gap energy) of the first guide layer and the Eg of the active layer (or the difference between the Eg of the second guide layer and the Eg of the active layer) is made 0.66 times or less of the difference between the Eg of the first cladding layer and the Eg of the active layer (or the difference between the Eg of the second cladding layer and the Eg of the active layer).Type: GrantFiled: October 19, 2006Date of Patent: October 30, 2007Assignee: Mitsubishi Electric CorporationInventors: Kimio Shigihara, Yoshihiko Hanamaki, Kimitaka Shibata, Kazushige Kawasaki
-
Patent number: 7259406Abstract: A semiconductor optical element having a includes an n-type GaAs buffer layer, an n-type AlGaInP cladding layer, a first InGaAsP (including zero As content)guide layer without added dopant impurities, an InGaAsP (including zero In content) active layer, a second InGaAsP (including zero As content)guide layer without added dopant impurities, a p-type AlGaInP cladding layer, a p-type band discontinuity reduction layer, and a p-type GaAs contact layer sequentially laminated on an n-type GaAs substrate C or Mg is the dopant impurity in the p-type GaAs contact layer, the p-type band discontinuity reduction layer, and the p-type AlGaInP cladding layer.Type: GrantFiled: November 2, 2005Date of Patent: August 21, 2007Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshihiko Hanamaki, Kenichi Ono, Kimio Shigihara, Kazushige Kawasaki, Kimitaka Shibata, Naoyuki Shimada
-
Publication number: 20070171948Abstract: An n-type first cladding layer, a first guide layer, a first enhancing layer, an active layer, a second enhancing layer, a second guide layer, and a p-type second cladding layer are sequentially stacked on an n-type GaAs substrate. The thickness of each of the first guide layer and the second guide layer is 100 nm or more. In such a semiconductor laser, the difference between the Eg (and gap energy) of the first guide layer and the Eg of the active layer (or the difference between the Eg of the second guide layer and the Eg of the active layer) is made 0.66 times or less of the difference between the Eg of the first cladding layer and the Eg of the active layer (or the difference between the Eg of the second cladding layer and the Eg of the active layer).Type: ApplicationFiled: October 19, 2006Publication date: July 26, 2007Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kimio Shigihara, Yoshihiko Hanamaki, Kimitaka Shibata, Kazushige Kawasaki
-
Publication number: 20060220037Abstract: A semiconductor optical element having a includes an n-type GaAs buffer layer, an n-type AlGaInP cladding layer, a first InGaAsP (including zero As content) guide layer without added dopant impurities, an InGaAsP (including zero In content) active layer, a second InGaAsP (including zero As content) guide layer without added dopant impurities, a p-type AlGaInP cladding layer, a p-type band discontinuity reduction layer, and a p-type GaAs contact layer sequentially laminated on an n-type GaAs substrate C or Mg is the dopant impurity in the p-type-GaAs contact layer, the p-type band discontinuity reduction layer, and the p-type AlGaInP cladding layer.Type: ApplicationFiled: November 2, 2005Publication date: October 5, 2006Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Yoshihiko Hanamaki, Kenichi Ono, Kimio Shigihara, Kazushige Kawasaki, Kimitaka Shibata, Naoyuki Shimada
-
Publication number: 20050286592Abstract: A semiconductor laser array device for outputting a higher power includes: a plurality of semiconductor laser chips, arranged in a predetermined pitch; a submount for mounting each semiconductor laser chip; and a heat sink for dissipating heat from the semiconductor laser chip through the submount; wherein a distance S between the centers of the chips and a thickness T of the submount satisfy the following inequality: 2×T?S?10×T, whereby improving efficiency of heat dissipation with a good process yield.Type: ApplicationFiled: March 14, 2005Publication date: December 29, 2005Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Naoyuki Shimada, Kimio Shigihara, Kazushige Kawasaki, Kimitaka Shibata, Tetsuya Yagi, Kenichi Ono, Hideki Haneda
-
Patent number: 5805629Abstract: A semiconductor device includes a p type InP substrate with a (001) surface; a mesa structure formed by dry etching, extending along a <110> direction, including semiconductor layers, having (110) side surfaces, and a height H.sub.m ; and mesa burying layers including a p type InP burying layer on the (110) side surfaces and the (001) surface, the p type InP burying layer having a thickness D.sub.p, and an n type InP burying layer on the p type InP burying layer. An angle between a (111)B surface and (001) surface is .theta..sub.111, the growth rates on the (110) side surfaces and on the (001) surface are respectively R.sub.g (110) and R.sub.g (001), an angle .theta. is tan .theta.=R.sub.g (110)/R.sub.g (001) and the critical thickness D.sub.n of the n type InP burying layer on the (001) surface when the n type InP burying layer is not grown on the (111)B surface is ##EQU1## The n type InP burying layer has a thickness D.ltoreq.D.sub.n.Type: GrantFiled: November 12, 1996Date of Patent: September 8, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masayoshi Takemi, Tatsuya Kimura, Daisuke Suzuki, Tetsuo Shiba, Kimitaka Shibata