Patents by Inventor Kimitoshi Niratsuka
Kimitoshi Niratsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9671293Abstract: A temperature detection circuit and a temperature measurement circuit capable of detecting and measuring temperatures precisely are disclosed. The temperature detection circuit includes n temperature detectors (n is an integer of 2 or more), each of the temperature detectors being configured to output a detection signal of high level when a temperature of an object reaches a first value, and a temperature determination part configured to determine whether or not the temperature of the object has reached a second value based on a count of high-level detection signals.Type: GrantFiled: November 24, 2014Date of Patent: June 6, 2017Assignee: Cypress Semiconductor CorporationInventors: Kazuhiro Kamiya, Kimitoshi Niratsuka
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Patent number: 9515603Abstract: A crystal oscillator start-up circuit capable of reducing a start-up time of a crystal oscillator is disclosed. The crystal oscillator start-up circuit is provided with a crystal oscillation unit including a crystal oscillator, a converter and an external oscillator. The crystal oscillation unit generates an output signal corresponding to the impedance characteristic of the crystal oscillator. The converter converts the output signal of the crystal oscillation unit to a voltage signal. The external oscillator outputs to the crystal oscillation unit an oscillation signal whose frequency is adjusted by the voltage signal to approach a resonance frequency of the crystal oscillator.Type: GrantFiled: October 14, 2014Date of Patent: December 6, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Yoshihiko Matsuo, Kimitoshi Niratsuka
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Publication number: 20160146675Abstract: A temperature detection circuit and a temperature measurement circuit capable of detecting and measuring temperatures precisely are disclosed. The temperature detection circuit includes n temperature detectors (n is an integer of 2 or more), each of the temperature detectors being configured to output a detection signal of high level when a temperature of an object reaches a first value, and a temperature determination part configured to determine whether or not the temperature of the object has reached a second value based on a count of high-level detection signals.Type: ApplicationFiled: November 24, 2014Publication date: May 26, 2016Applicant: Spansion LLCInventors: Kazuhiro KAMIYA, Kimitoshi Niratsuka
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Publication number: 20160105147Abstract: A crystal oscillator start-up circuit capable of reducing a start-up time of a crystal oscillator is disclosed. The crystal oscillator start-up circuit is provided with a crystal oscillation unit including a crystal oscillator, a converter and an external oscillator. The crystal oscillation unit generates an output signal corresponding to the impedance characteristic of the crystal oscillator. The converter converts the output signal of the crystal oscillation unit to a voltage signal. The external oscillator outputs to the crystal oscillation unit an oscillation signal whose frequency is adjusted by the voltage signal to approach a resonance frequency of the crystal oscillator.Type: ApplicationFiled: October 14, 2014Publication date: April 14, 2016Inventors: Yoshihiko MATSUO, Kimitoshi NIRATSUKA
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Patent number: 9263988Abstract: A crystal oscillation circuit is provided with a crystal oscillator, an inverter unit coupled in parallel with the crystal oscillator and including a plurality of inverters, a current supply unit that supplies current to at least a first inverter of the plurality of inverters, a signal converter that supplies current to at least a last inverter of the plurality of inverters and outputs a voltage to an external circuit, and a current controller that makes the current supply unit provide current corresponding to a voltage level of the output voltage of the signal converter. The crystal oscillation circuit is capable of reducing power consumption.Type: GrantFiled: July 30, 2014Date of Patent: February 16, 2016Assignee: Cypress Semiconductor CorporationInventors: Kimitoshi Niratsuka, Shingo Sakamoto
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Publication number: 20160036383Abstract: A crystal oscillation circuit is provided with a crystal oscillator, an inverter unit coupled in parallel with the crystal oscillator and including a plurality of inverters, a current supply unit that supplies current to at least a first inverter of the plurality of inverters a signal converter that supplies current to at least a last inverter of the plurality of inverters and outputs a voltage to an external circuit, and a current controller that makes the current supply unit provide current corresponding to a voltage level of the output voltage of the signal converter. The crystal oscillation circuit is capable of reducing power consumption.Type: ApplicationFiled: July 30, 2014Publication date: February 4, 2016Applicant: Spansion LLCInventors: Kimitoshi Niratsuka, Shingo Sakamoto
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Patent number: 9235672Abstract: An analysis unit analyzes a source code representing design data of a semiconductor device, and generates information (CDFG information) indicating the data and control flow of the semiconductor device. A high-level synthesis data generation unit acquires intermediate data (an object file), which is obtained by compiling the source code, generates intermediate data (an object file) by incorporating the CDFG information generated by the analysis unit into the acquired intermediate data, and outputs the generated intermediate data as high-level synthesis data.Type: GrantFiled: August 22, 2014Date of Patent: January 12, 2016Assignee: SOCIONEXT INC.Inventors: Atsushi Yasunaka, Kimitoshi Niratsuka
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Publication number: 20150106774Abstract: An analysis unit analyzes a source code representing design data of a semiconductor device, and generates information (CDFG information) indicating the data and control flow of the semiconductor device. A high-level synthesis data generation unit acquires intermediate data (an object file), which is obtained by compiling the source code, generates intermediate data (an object file) by incorporating the CDFG information generated by the analysis unit into the acquired intermediate data, and outputs the generated intermediate data as high-level synthesis data.Type: ApplicationFiled: August 22, 2014Publication date: April 16, 2015Inventors: Atsushi YASUNAKA, Kimitoshi NIRATSUKA
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Patent number: 7405627Abstract: In a PLL frequency synthesizer outputting signals with different frequencies: voltage-controlled oscillators output the signals and have the oscillation frequencies controlled according to control voltages; a first switch selects one of the signals; a frequency divider generates a frequency-divided signal of the selected signal by use of a changeable frequency-division ratio; a phase comparator generates the phase difference between the frequency-divided signal and a reference signal; a second switch selects one of paths connected to low-pass filters; each low-pass filter is provided for one of the voltage-controlled oscillators, has a changeable time constant, and converts the phase difference into one of the control voltages; and a controller cyclically controls the first and second switches and the frequency divider so that the voltage-controlled oscillators continuously output the signals, and changes the changeable time constant of each low-pass filter after all of the signals become stable.Type: GrantFiled: March 6, 2007Date of Patent: July 29, 2008Assignee: Fujitsu LimitedInventors: Katsuya Shimomura, Kimitoshi Niratsuka
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Patent number: 7342436Abstract: A reduced-size bipolar supply voltage generator which produces a positive and negative voltages from a unipolar power source. A single inductor is employed for current switching operation, where electric energy supplied from a power source is stored in magnetic form, and the stored magnetic energy is released as electric energy. A first and second diodes are connected to first and second ends of the inductor, respectively. The inductor is grounded at the first end via a first switch, while its second end is connected to the power source via a second switch. A switching controller activates both switches to energize the inductor. It then deactivates the first switch alone, thus directing the inductor's energy to the positive voltage output through the first diode. The controller may turn off the second switch alone after energizing the inductor. The stored energy now appears at the negative voltage output through the second diode.Type: GrantFiled: December 12, 2002Date of Patent: March 11, 2008Assignee: Fujitsu LimitedInventors: Chikara Tsuchiya, Kimitoshi Niratsuka, Eiji Nishimori, Katsuyoshi Otsu
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Publication number: 20070152758Abstract: In a PLL frequency synthesizer outputting signals with different frequencies: voltage-controlled oscillators output the signals and have the oscillation frequencies controlled according to control voltages; a first switch selects one of the signals; a frequency divider generates a frequency-divided signal of the selected signal by use of a changeable frequency-division ratio; a phase comparator generates the phase difference between the frequency-divided signal and a reference signal; a second switch selects one of paths connected to low-pass filters; each low-pass filter is provided for one of the voltage-controlled oscillators, has a changeable time constant, and converts the phase difference into one of the control voltages; and a controller cyclically controls the first and second switches and the frequency divider so that the voltage-controlled oscillators continuously output the signals, and changes the changeable time constant of each low-pass filter after all of the signals become stable.Type: ApplicationFiled: March 6, 2007Publication date: July 5, 2007Applicant: FUJITSU LIMITEDInventors: Katsuya Shimomura, Kimitoshi Niratsuka
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Patent number: 6876185Abstract: On a semiconductor device 20, fabricated are a VCO 10A, an frequency divider by integer R 21, a frequency divider by integer (P×N+A) 22 wherein each of P, N and A is an integer, A is variable and A<N, a phase comparator 23, and a charge pump 24. A low pass filter 25 having been confirmed to have standard characteristics is externally added to the semiconductor device 20 to construct a PLL circuit to be tested. The frequency divider 22 is of a pulse swallow type and has a control input for setting the integer A at ones in the vicinity of a value in normal use by user. The control input is connected to external terminals D0 and D1 of the semiconductor device 20 for simplifying a test. The semiconductor device 20 is judged whether it is acceptable or not in quality by checking whether or not the PLL circuit enters into a locked state within a given period in each cases of A=A1 and A=A2, where A1<A0<A2 and A0 is a value in normal use by user.Type: GrantFiled: June 3, 2003Date of Patent: April 5, 2005Assignee: Fujitsu LimitedInventor: Kimitoshi Niratsuka
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Publication number: 20030201786Abstract: On a semiconductor device 20, fabricated are a VCO 10A, an frequency divider by integer R 21, a frequency divider by integer (P×N+A) 22 wherein each of P, N and A is an integer, A is variable and A<N, a phase comparator 23, and a charge pump 24. A low pass filter 25 having been confirmed to have standard characteristics is externally added to the semiconductor device 20 to construct a PLL circuit to be tested. The frequency divider 22 is of a pulse swallow type and has a control input for setting the integer A at ones in the vicinity of a value in normal use by user. The control input is connected to external terminals D0 and D1 of the semiconductor device 20 for simplifying a test. The semiconductor device 20 is judged whether it is acceptable or not in quality by checking whether or not the PLL circuit enters into a locked state within a given period in each cases of A=A1 and A=A2, where A1<A0<A2 and A0 is a value in normal use by user.Type: ApplicationFiled: June 3, 2003Publication date: October 30, 2003Applicant: Fujitsu LimitedInventor: Kimitoshi Niratsuka
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Patent number: 6597162Abstract: On a semiconductor device 20, fabricated are a VCO 10A, an frequency divider by integer R 21, a frequency divider by integer (P×N+A) 22 wherein each of P, N and A is an integer, A is variable and A<N, a phase comparator 23, and a charge pump 24. A low pass filter 25 having been confirmed to have standard characteristics is externally added to the semiconductor device 20 to construct a PLL circuit to be tested. The frequency divider 22 is of a pulse swallow type and has a control input for setting the integer A at ones in the vicinity of a value in normal use by user. The control input is connected to external terminals D0 and D1 of the semiconductor device 20 for simplifying a test. The semiconductor device 20 is judged whether it is acceptable or not in quality by checking whether or not the PLL circuit enters into a locked state within a given period in each cases of A=A1 and A=A2, where A1<A0<A2 and A0 is a value in normal use by user.Type: GrantFiled: January 11, 2001Date of Patent: July 22, 2003Assignee: Fujitsu LimitedInventor: Kimitoshi Niratsuka
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Publication number: 20030117209Abstract: A reduced-size bipolar supply voltage generator which produces a positive and negative voltages from a unipolar power source. A single inductor is employed for current switching operation, where electric energy supplied from a power source is stored in magnetic form, and the stored magnetic energy is released as electric energy. A first and second diodes are connected to first and second ends of the inductor, respectively. The inductor is grounded at the first end via a first switch, while its second end is connected to the power source via a second switch. A switching controller activates both switches to energize the inductor. It then deactivates the first switch alone, thus directing the inductor's energy to the positive voltage output through the first diode. The controller may turn off the second switch alone after energizing the inductor. The stored energy now appears at the negative voltage output through the second diode.Type: ApplicationFiled: December 12, 2002Publication date: June 26, 2003Applicant: FUJITSU LIMITEDInventors: Chikara Tsuchiya, Kimitoshi Niratsuka, Eiji Nishimori, Katsuyoshi Otsu
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Patent number: 6366767Abstract: A local oscillation circuit comprising a crystal oscillating circuit for generating an output voltage having a constant frequency, and an interface part for converting the output voltage from the crystal oscillating circuit into a current signal, the current signal being used as a local oscillation signal to be mixed with the receiving signal from an antenna, whereby a receiving circuit, which can be made as a single semiconductor chip consuming little current, can be realized.Type: GrantFiled: May 11, 1999Date of Patent: April 2, 2002Assignee: Fujitsu LimitedInventors: Kimitoshi Niratsuka, Kunihiko Gotoh
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Patent number: 6317476Abstract: A device for suppressing spurious signals generated by a fractional-N synthesizer. The fractional-N synthesizer generates an output frequency where an underlying PLL circuit uses a frequency divider for dividing the output frequency by a frequency-division ratio to obtain a comparison frequency and performs phase-comparison operations between a reference frequency and the comparison frequency to control the output frequency. The output frequency is changed by a frequency interval smaller than the reference frequency by making a temporal change to the frequency-division ratio once in every predetermined number of cycles.Type: GrantFiled: August 31, 1998Date of Patent: November 13, 2001Assignee: Fujitsu LimitedInventors: Kazuaki Oishi, Kimitoshi Niratsuka
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Publication number: 20010028243Abstract: On a semiconductor device 20, fabricated are a VCO 10A, an frequency divider by integer R 21, a frequency divider by integer (P×N+A) 22 wherein each of P, N and A is an integer, A is variable and A<N, a phase comparator 23, and a charge pump 24. A low pass filter 25 having been confirmed to have standard characteristics is externally added to the semiconductor device 20 to construct a PLL circuit to be tested. The frequency divider 22 is of a pulse swallow type and has a control input for setting the integer A at ones in the vicinity of a value in normal use by user. The control input is connected to external terminals D0 and D1 of the semiconductor device 20 for simplifying a test. The semiconductor device 20 is judged whether it is acceptable or not in quality by checking whether or not the PLL circuit enters into a locked state within a given period in each cases of A=A1 and A=A2, where A1<A0<A2 and A0 is a value in normal use by user.Type: ApplicationFiled: January 11, 2001Publication date: October 11, 2001Applicant: FUJITSU LIMITEDInventor: Kimitoshi Niratsuka
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Patent number: 5818303Abstract: A fractional N-frequency synthesizer includes an accumulator outputting an output value, and a spurious signal cancel circuit. The spurious signal cancel circuit includes a pulse forming circuit, receiving a spurious signal cancelling reference signal, a reset signal and the output value of the accumulator, and outputting, in synchronism with the spurious signal cancelling reference signal, a pulse voltage signal having a pulse width proportional to the output value of the accumulator from a time when the reset signal is received, and a constant current circuit controlled by the pulse voltage signal and outputting an output current of the spurious signal cancel circuit.Type: GrantFiled: July 24, 1997Date of Patent: October 6, 1998Assignee: Fujitsu LimitedInventors: Kazuaki Oishi, Kimitoshi Niratsuka
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Patent number: 5640110Abstract: A current supply circuit includes a current source producing a first current, a current amplifying circuit for producing a second current having a magnitude a.multidot.I/h.sub.FE from the first current where a is a constant, I is a magnitude of the first current and h.sub.FE is a current transfer ratio of a current supply circuit. The above current supply circuit produces a third current from the second current so that the third current has a magnitude equal to a.multidot.I.Type: GrantFiled: October 5, 1995Date of Patent: June 17, 1997Inventors: Kimitoshi Niratsuka, Yosiaki Sano