Abstract: A semiconductor device includes: a semiconductor substrate; a first semiconductor layer; a first conductor; a first power supply line; a second power supply line; and a circuit. The semiconductor substrate has a first surface, a second surface facing the first surface, and a third surface disposed between the first surface and the second surface. The first semiconductor layer is disposed along the first surface from the third surface. The first conductor is disposed on the first semiconductor layer. The first power supply line is electrically connected to the first conductor. The second power supply line is electrically connected to the semiconductor substrate. The circuit is disposed on the semiconductor substrate and connected to the first power supply line and the second power supply line.

Abstract: A semiconductor device includes: a semiconductor substrate; a first semiconductor layer; a first conductor; a first power supply line; a second power supply line; and a circuit. The semiconductor substrate has a first surface, a second surface facing the first surface, and a third surface disposed between the first surface and the second surface. The first semiconductor layer is disposed along the first surface from the third surface. The first conductor is disposed on the first semiconductor layer. The first power supply line is electrically connected to the first conductor. The second power supply line is electrically connected to the semiconductor substrate. The circuit is disposed on the semiconductor substrate and connected to the first power supply line and the second power supply line.

Abstract: A semiconductor device comprises a channel body, a pair of source drain regions provided on the channel body and a gate electrode provided above a part of the channel body between the source drain regions. The semiconductor device further comprises a first insulating layer covering the source drain regions and the gate electrode; contact bodies extending in the first insulating layer electrically connected to the source drain regions respectively; and a silicide layer provided between one of the source drain regions and one of the contact bodies electrically connected thereto. The one of the contact bodies includes a main part extending in the first insulating layer, and an expanded portion expanded along a surface of the one of the source drain regions; and the silicide layer is positioned between the expanded portion and the one of the source drain regions.

Abstract: According to one embodiment, a semiconductor device includes an element isolation insulating film, a gate electrode film, source/drain regions, a channel region, and an air gap. The element isolation insulating film partitions an element arrangement area on one main face side of a semiconductor substrate. The channel region is disposed near a surface of the semiconductor substrate below the gate electrode film. The air gap is disposed at a region of the element isolation insulating film contacting with the channel region.

Abstract: According to one embodiment, a semiconductor device includes an element isolation insulating film, a gate electrode film, source/drain regions, a channel region, and an air gap. The element isolation insulating film partitions an element arrangement area on one main face side of a semiconductor substrate. The channel region is disposed near a surface of the semiconductor substrate below the gate electrode film. The air gap is disposed at a region of the element isolation insulating film contacting with the channel region.

Abstract: A semiconductor device according to an embodiment comprises: a field effect transistor comprising a semiconductor layer and a gate electrode; a wiring line layer positioned above the field effect transistor; and a control circuit that adjusts a voltage of a wiring line in the wiring line layer. The wiring line layer comprises: a contact wiring line connected to a source or a drain of the field effect transistor; and a first wiring line facing a position between the gate electrode and the contact wiring line, of the semiconductor layer. The control circuit adjusts the contact wiring line to a certain voltage and sets the first wiring line to a floating state.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate made of a first semiconductor material, an element isolation insulating film, a gate electrode film, source/drain regions, a channel region, and a diffusion preventing film. The channel region is provided near a surface of the semiconductor substrate below the gate electrode film, and containing a second impurity of a predetermined conductivity type diffused therein. The diffusion preventing film is provided at an interface between the element isolation insulating film and the semiconductor substrate, and made of a second semiconductor material different from the first semiconductor material.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate made of a first semiconductor material, an element isolation insulating film, a gate electrode film, source/drain regions, a channel region, and a diffusion preventing film. The channel region is provided near a surface of the semiconductor substrate below the gate electrode film, and containing a second impurity of a predetermined conductivity type diffused therein. The diffusion preventing film is provided at an interface between the element isolation insulating film and the semiconductor substrate, and made of a second semiconductor material different from the first semiconductor material.

Abstract: A semiconductor device according to an embodiment includes a first transistor and a second transistor. The first transistor is connected to a first wiring through a wiring plug made of a material having a first resistance value smaller than a predetermined value. In addition, at least any one of a drain and a source of the second transistor is connected to a second wiring through a polysilicon plug made of a material having a second resistance value larger than the first resistance value.

Abstract: A semiconductor device according to an embodiment comprises: a field effect transistor comprising a semiconductor layer and a gate electrode; a wiring line layer positioned above the field effect transistor; and a control circuit that adjusts a voltage of a wiring line in the wiring line layer. The wiring line layer comprises: a contact wiring line connected to a source or a drain of the field effect transistor; and a first wiring line facing a position between the gate electrode and the contact wiring line, of the semiconductor layer. The control circuit adjusts the contact wiring line to a certain voltage and sets the first wiring line to a floating state.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell; and a peripheral transistor. The memory cell includes a first channel, a first insulating film provided on the first channel, a charge storage film provided on the first insulating film, a second insulating film provided on the charge storage film, a first semiconductor film provided on the second insulating film, and a first electrode film provided on the first semiconductor film and containing a metal. The peripheral transistor includes a second channel, a third insulating film provided on the second channel, a second semiconductor film provided on the third insulating film, a fourth insulating film provided on the second semiconductor film, a third semiconductor film provided on the second semiconductor film and a side surface of the fourth insulating film, and a second electrode film.

Abstract: A semiconductor device in one embodiment includes a semiconductor substrate, a fin disposed on a surface of the semiconductor substrate, an insulator including a gate insulator disposed on a side surface of the fin, and a gate electrode disposed on the insulator that is disposed on side surfaces of the fin and an upper surface of the fin. The device further includes a plurality of epitaxial stripe shaped layers disposed horizontally on the side surface of the fin at different heights, and an interlayer dielectric disposed on the semiconductor substrate to cover the fin and applying a stress to the fin and the epitaxial layers. Any two adjacent epitaxial layers along the fin height direction determine a gap and the gaps between adjacent layers increase or decrease with increasing distance from the substrate.

Abstract: A semiconductor device in one embodiment includes a semiconductor substrate, a fin disposed on a surface of the semiconductor substrate, an insulator including a gate insulator disposed on a side surface of the fin, and a gate electrode disposed on the insulator that is disposed on side surfaces of the fin and an upper surface of the fin. The device further includes a plurality of epitaxial stripe shaped layers disposed horizontally on the side surface of the fin at different heights, and an interlayer dielectric disposed on the semiconductor substrate to cover the fin and applying a stress to the fin and the epitaxial layers. Any two adjacent epitaxial layers along the fin height direction determine a gap and the gaps between adjacent layers increase or decrease with increasing distance from the substrate.

Abstract: A semiconductor device in one embodiment includes a semiconductor substrate, a fin disposed on a surface of the semiconductor substrate, an insulator including a gate insulator disposed on a side surface of the fin, and a gate electrode disposed on the insulator that is disposed on side surfaces of the fin and an upper surface of the fin. The device further includes a plurality of epitaxial stripe shaped layers disposed horizontally on the side surface of the fin at different heights, and an interlayer dielectric disposed on the semiconductor substrate to cover the fin and applying a stress to the fin and the epitaxial layers. Any two adjacent epitaxial layers along the fin height direction determine a gap and the gaps between adjacent layers increase or decrease with increasing distance from the substrate.

Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes a step of forming a dummy-fin semiconductor on a semiconductor substrate; a step of forming an insulating layer, into which a lower part of the dummy-fin semiconductor is buried, on the semiconductor substrate; a step of forming a fin semiconductor, which is bonded to a side face at an upper part of the dummy-fin semiconductor, on the insulating layer; and a step of removing the dummy-fin semiconductor on the insulating layer with the fin semiconductor being left on the insulating layer.

Abstract: According to one embodiment, a semiconductor device includes a channel region formed on a first side surface of a fin-type semiconductor and a source/drain region formed on a second side surface, plane orientation of which is different from that of the first side surface, so that the channel region is interposed in the fin-type semiconductor.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, and a fin disposed on a surface of the semiconductor substrate. The device further includes a gate insulator disposed on a side surface of the fin, and a gate electrode disposed on the side surface and an upper surface of the fin via the gate insulator. The device further includes epitaxial layers disposed on the side surface of the fin in order along a fin height direction, and an interlayer dielectric disposed on the semiconductor substrate to cover the fin and applying a stress to the fin and the epitaxial layers. A spacing of a gap between the epitaxial layers adjacent in the fin height direction, and a spacing of a gap between the lowermost epitaxial layer and a bottom surface of the interlayer dielectric change in accordance with heights at which the gaps are located.

Abstract: According to one embodiment, a semiconductor device includes: a fin formed on a semiconductor substrate; a piezoelectric element that applies stress to the fin; a gate electrode that applies voltage to the fin and the piezoelectric element; and source/drain regions formed on the fin so as to sandwich a channel region formed on the fin.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, and a fin disposed on a surface of the semiconductor substrate and having a side surface of a (110) plane. The device further includes a gate insulator disposed on the side surface of the fin, and a gate electrode disposed on the side surface and an upper surface of the fin via the gate insulator. The device further includes a plurality of epitaxial layers disposed on the side surface of the fin in order along a height direction of the fin.

Abstract: According to the embodiments, a semiconductor device includes a first semiconductor layer which has a projection extending along a surface of the first semiconductor layer. A gate electrode is over a surface of the projection with an intervening gate insulator. A second semiconductor layer on a portion of the side surface of the projection other than a portion covered with the gate electrode has a trench. A source/drain area is formed in the second semiconductor layer. A silicide film is over a surface of the second semiconductor layer including a surface in the trench. A conductive plug contacts the silicide film.