Abstract: A semiconductor device has memory cells, a bias circuit and a charging circuit. A conductive or non-conductive state of the memory cells is read out by the bias circuit and the charging circuit as data in the memory cells. The device also includes a control circuit having a supply voltage detection circuit in which a first N-channel depletion-mode MOSFET whose drain and gate electrodes are connected in common, and a second N-channel depletion-mode MOSFET whose source and gate electrodes are connected in common, are connected in series between the power supply terminal and the ground potential terminal. The series junction node formed between the first and second MOSFETs is connected to one input terminal of a NOR gate while an inverted signal line for a semiconductor device enabling signal is connected to the other input terminal, and an output terminal of the NOR gate is connected to an input terminal of an inverter, an output of the inverter being used as a control signal for enabling the charging circuit.

Abstract: A word line driver incorporated in a semiconductor memory device is powered by an internal step-down voltage generator for energizing a selected word line, and an address transition detecting circuit causes an n-channel enhancement type switching transistor to temporally turn on between the address transition and completion of a charging operation on the selected word line, thereby preventing the internal step-down power voltage from undesirable decay.

Abstract: A semiconductor memory whose sense amplifier having a bias circuit and a charging circuit is provided. The bias circuit includes a first MOSFET whose source is connected to a digit line, a second MOSFET provided between a power source and the first MOSFET and becoming a load of the first MOSFET, and a first inverter whose input terminal and output terminal are connected respectively to the source and gate of the first MOSFET. The charging circuit includes a third MOSFET whose source is connected to the source of the first MOSFET, a second inverter whose input terminal and output terminal are connected respectively to the source and gate of the third MOSFET, and a fourth MOSFET provided between the drain of the third MOSFET and the power source and receiving through the gate thereof an output signal of an address transition detector which detects an address change and generates a pulse signal.