Patents by Inventor Kimmo K. Kuusilinna

Kimmo K. Kuusilinna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9069663
    Abstract: A method for optimizing memory bandwidth using bank-based memory allocation is described. The method includes receiving a request for an allocation of memory. In response to receiving the request, memory is allocated to the request based on a performance ranking of memory banks in a plurality of memory banks. A performance ranking of a particular memory bank may be based at least in part on both a busyness and a row hit ratio of the particular memory bank. Apparatus and computer readable media are also described.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: June 30, 2015
    Assignee: Memory Technologies LLC
    Inventors: Eero T. Aho, Kimmo K. Kuusilinna, Jari A. Nikara
  • Publication number: 20140337599
    Abstract: A method for optimizing memory bandwidth using bank-based memory allocation is described. The method includes receiving a request for an allocation of memory. In response to receiving the request, memory is allocated to the request based on a performance ranking of memory banks in a plurality of memory banks. A performance ranking of a particular memory bank may be based at least in part on both a busyness and a row hit ratio of the particular memory bank. Apparatus and computer readable media are also described.
    Type: Application
    Filed: July 23, 2014
    Publication date: November 13, 2014
    Inventors: Eero T. Aho, Kimmo K. Kuusilinna, Jari A. Nikara
  • Patent number: 8819379
    Abstract: A method for optimizing memory bandwidth using bank-based memory allocation is described. The method includes receiving a request for an allocation of memory. In response to receiving the request, memory is allocated to the request based on a performance ranking of memory banks in a plurality of memory banks. A performance ranking of a particular memory bank may be based at least in part on both a busyness and a row hit ratio of the particular memory bank. Apparatus and computer readable media are also described.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: August 26, 2014
    Assignee: Memory Technologies LLC
    Inventors: Eero T. Aho, Kimmo K. Kuusilinna, Jari A. Nikara
  • Patent number: 8713248
    Abstract: A dynamic random access memory integrated circuit includes an interface to a serial interconnect, where the interface is configured to receive a plurality of memory access instructions over the serial interconnect, and a buffer configured to store the plurality of memory access instructions prior to execution of the buffered memory access instructions by the dynamic random access memory integrated circuit. The memory access instructions are received over at least one serial link that forms the serial interconnect, and the at least one serial link may be a shared bi-directional serial link or a uni-directional serial link.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: April 29, 2014
    Assignee: Nokia Corporation
    Inventors: Eero T. Aho, Kimmo K. Kuusilinna, Jari A. Nikara
  • Publication number: 20130124815
    Abstract: A method for optimizing memory bandwidth using bank-based memory allocation is described. The method includes receiving a request for an allocation of memory. In response to receiving the request, memory is allocated to the request based on a performance ranking of memory banks in a plurality of memory banks. A performance ranking of a particular memory bank may be based at least in part on both a busyness and a row hit ratio of the particular memory bank. Apparatus and computer readable media are also described.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 16, 2013
    Inventors: Eero T. Aho, Kimmo K. Kuusilinna, Jari A. Nikara
  • Publication number: 20100306458
    Abstract: A dynamic random access memory integrated circuit includes an interface to a serial interconnect, where the interface is configured to receive a plurality of memory access instructions over the serial interconnect, and a buffer configured to store the plurality of memory access instructions prior to execution of the buffered memory access instructions by the dynamic random access memory integrated circuit. The memory access instructions are received over at least one serial link that forms the serial interconnect, and the at least one serial link may be a shared bi-directional serial link or a uni-directional serial link.
    Type: Application
    Filed: June 2, 2009
    Publication date: December 2, 2010
    Inventors: Eero T. Aho, Kimmo K. Kuusilinna, Jari A. Nikara