Patents by Inventor Kimmo Kuusilinna

Kimmo Kuusilinna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080084725
    Abstract: Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically.
    Type: Application
    Filed: October 5, 2006
    Publication date: April 10, 2008
    Inventors: Vesa Lahtinen, Tapio Hill, Kimmo Kuusilinna, Jari Nikara, Mika Kuulusa, Tommi Makelainen
  • Publication number: 20080086603
    Abstract: Systems, apparatuses and methods for efficient logical memory management using centralized memory management. One embodiment involves allocating a first memory region to a first subsystem, generating a region code associated with the allocated memory region, storing the region code in connection with an address of the memory region, and defining the first subsystem as a first owner for the memory region by storing a unique subsystem identifier together with the region code in a parameter table. In this manner, a memory region may be globally addressed by its region code and an ownership to a subsystem is defined and stored.
    Type: Application
    Filed: October 5, 2006
    Publication date: April 10, 2008
    Inventors: Vesa Lahtinen, Kimmo Kuusilinna, Jari Nikara, Jukka M. Nurminen
  • Publication number: 20070242233
    Abstract: A projector screen is shown comprising one or more markers arranged to be used by projection processing circuitry to calculate a user perceived distortion in an image to be projected on the projector screen. A related method, computer program and projection processing circuitry are also shown.
    Type: Application
    Filed: April 13, 2006
    Publication date: October 18, 2007
    Inventors: Tomi Sokeila, Tapani Leppanen, Mika Pesonen, Kimmo Kuusilinna, Aki Launiainen
  • Publication number: 20040153592
    Abstract: A method for adapting a bus to data traffic in a system comprising several functional units (311, 312, . . . , 31n) and a bus structure. The functional units are divided into at least two sets so that units, which mainly transfer data with each other belong to a same set and are interfaced with the same separate sub-bus (321; 322). The sub-buses can be united by switches (SW) into a more extensive bus, which is only used when data must be transferred between different sets. Supply voltage of each sub-bus is adjustable and is set the lower the less traffic there is on the bus. The parallel transfer operation makes it possible to increase the transfer capacity of the bus structure without increasing it's clock frequency. Furthermore energy consumption can be reduced by dropping the supply voltage of the bus circuits so that the bus retains the transfer capacity needed.
    Type: Application
    Filed: December 12, 2003
    Publication date: August 5, 2004
    Applicant: Nokia Corporation
    Inventors: Jari Parviainen, Timo Hamalainen, Kimmo Kuusilinna