Abstract: A circuit for a high speed digital multiplexer has an active load circuit connected to an output of the digital multiplexer. The active load circuit loads the multiplexer output with a transimpedance stage with low input resistance to reduce the RC time constant at the multiplexer output. The active load circuit may be based on two active devices connected to the multiplexer output so as to form a differential cascode circuit.

Abstract: In a circuit having two input stages multiplexed to a common output stage having an output, one of the two input stages including transistor having a base, a collector and an emitter; a method of protecting the transistor from ?-degradation when the one of the two input stages is disabled comprises: clamping the base to a substantially fixed voltage for a first range of voltages applied to the one of the two input stages; and bootstrapping the base to a voltage that follows the output for a second range of voltages applied to the one of the two input stages. Alternatively, a method of protecting a transistor having a base connected through a finite impedance to an input voltage, a collector and an emitter, may comprise bootstrapping the base to a voltage that follows the input voltage with an offset when the input voltage is within a second range of voltages.

Abstract: In a circuit having two input stages multiplexed to a common output stage having an output, one of the two input stages including transistor having a base, a collector and an emitter; a method of protecting the transistor from &bgr;-degradation when the one of the two input stages is disabled comprises: clamping the base to a substantially fixed voltage for a first range of voltages applied to the one of the two input stages; and bootstrapping the base to a voltage that follows the output for a second range of voltages applied to the one of the two input stages. Alternatively, a method of protecting a transistor having a base connected through a finite impedance to an input voltage, a collector and an emitter, may comprise bootstrapping the base to a voltage that follows the input voltage with an offset when the input voltage is within a second range of voltages.

Abstract: An output distortion correction amplifier system includes an input stage; a current mirror connected to the input stage; an output stage having its input connected to the input stage and a current mirror and its output connected to the input stage; a compensation impedance connected to the input of the output stage; and a distortion correction circuit for directly sensing the distortion voltage across the output stage and providing to the current mirror a current representative of the distortion voltage for delivering to the compensation impedance a correction current to develop a correction voltage at the input of the output stage to nullify the effect of the distortion voltage.

Abstract: An output distortion correction amplifier system includes an input stage; a current mirror connected to the input stage; an output stage having its input connected to the input stage and a current mirror and its output connected to the input stage; a compensation impedance connected to the input of the output stage; and a distortion correction circuit for directly sensing the distortion voltage across the output stage and providing to the current mirror a current representative of the distortion voltage for delivering to the compensation impedance a correction current to develop a correction voltage at the input of the output stage to nullify the effect of the distortion voltage.

Abstract: An input distortion correction current-feedback amplifier system includes a current mirror; an input stage connected to the input of the current mirror; an output stage connected to the output of the current mirror; a feedback circuit connected from the output stage to the input stage; a compensation impedance connected to the output of the current mirror; and a distortion correction circuit for sensing the distortion voltage across the input stage and providing to the current mirror a current representative of the distortion voltage for delivering to the compensation impedance a correction current to develop a correction voltage at the input of the output stage to nullify the effect of the distortion voltage.

Abstract: A selectable input buffer control system includes at least one input buffer; a plurality of input receivers associated with each input buffer; an addresser circuit for addressing each input receiver; and a selection circuit associated with each input buffer for enabling its associated input buffer in response to the addressing of any one or more of the input receivers associated with that input buffer.

Abstract: A logic buffer includes a logic gate having at least two input terminals and two output nodes, a plurality of output terminals, each having a capacitance associated therewith and a pull-up circuit interconnected between each output node and the plurality of output terminals for alternately charging the capacitance of each output terminal. The buffer also includes a differential pull-down circuit including a common pull-down current source, the pull-down device interconnected between the output nodes and the output terminals for inversely alternately discharging the capacitances through the common pull-down current source for accelerating the discharge of the capacitance of the respective output terminal.

Abstract: A non-inverting feedback amplifier with high disabled impedance includes a disableable signal amplifier; a feedback network having an input node, a feedback node and a reference node; the signal amplifier having a first input for receiving an input signal and a second input for receiving a feedback signal from the feedback node; and a reference buffer including a reference amplifier with its output directly connected to the reference node without additional series switching elements, a first input connected to a reference voltage, and a second input connected to its own output for mirroring at its output the reference voltage at its first input when the reference buffer and signal amplifier are enabled and presenting a high impedance between the feedback network and the reference voltage when the signal amplifier and reference buffer are disabled.

Abstract: An Early voltage and beta current compensated cascode current mirror includes a cascode current mirror having an input stage responsive to an input current, a current mirror circuit having a first stage responsive to the input stage and a second stage responsive to the first stage, and an output stage responsive to the second stage for providing an output voltage and current; and a compensation circuit, responsive to the cascode current mirror, having a first compensation stage, a second compensation stage and a bootstrapping buffer, the first compensation stage, in response to a change in the output voltage, impressing a corresponding change in voltage on the second compensation stage, the second compensation stage thereby providing a change in current to the cascode current mirror for cancelling current errors induced by base current modulation in the output stage, the bootstrapping buffer, in response to the change in voltage, impressing a corresponding change in voltage on the first compensation stage to

Abstract: A fast, low output impedance, low-power clamp circuit for a switched complementary emitter follower includes a current mirror circuit and two transistors. In operation, high current is provided to allow for fast switching when turning off the complementary emitter follower. When the complementary emitter follower has been turned off, the clamp circuit reverts to low-power operation requiring much lower current while maintaining the complementary emitter follower in the off condition.

Abstract: A switched-transconductance circuit used in a multiplexer forming a part of a crosspoint switch includes integrated T-switches that are enabled when the transconductance stage is not enabled. The transconductance stage is selectively enabled by controlling a split-tail current source driving a differential pair of input transistors. When the transconductance stage is disabled (1) a pair of switches connected between the collectors of the differential pair and a positive voltage supply node are enabled, (2) a pair of cascode transistors connected between the collectors of the differential pair and output leads of the circuit are reversed biased by the positive supply voltage passing through the pair of switches, and (3) a switch is enabled between a common emitter node of the differential pair and a low impedance constant voltage node.

Abstract: A high impedance node of a transimpedance stage drives the input of a unity-gain forward buffer. A unity-gain integrated back-buffer is enabled to drive the high-impedance node from the output of the forward buffer when the forward buffer is disabled. A voltage from the forward buffer limits the reverse-biasing of all transistors in the back-buffer when the back buffer is disabled, and a voltage from the back-buffer limits the reverse-biasing of all transistors in the forward buffer when the forward buffer is disabled. The output-driver transistors of the forward buffer are bootstrapped to the output voltage through resistors which, when the forward buffer is enabled, bias pre-driver transistor coupled to the output-driver transistors. Neither the forward buffer nor the back-buffer consume a significant amount of power when not enabled.