Abstract: A multi-bit flip-flop (MBFF) has flip-flops connected to form an internal scan chain. One of the flip-flops outputs a first data-out signal at a first data output terminal of the MBFF, and includes a selection circuit, a latch-based circuit, and a data-out stage circuit. The selection circuit transmits a data signal or a test signal to an output node of the selection circuit to serve as an input signal. The latch-based circuit generates a first signal according to the input signal. The data-out stage circuit receives the first signal, and generates the data-out signal according to the first signal. When the MBFF operates in a test mode, the selection circuit transmits the test signal to serve as the input signal, and the data-out stage circuit keeps the data-out signal at a fixed voltage level regardless of a voltage level of the test signal.

Abstract: A clock gating cell is provided. The clock gating cell includes an input stage and an output stage. The input stage receives a first clock signal and at least one input enable signal and generates a first enable signal corresponding to one of the least one input enable signal according to the first clock signal. The output stage is coupled to the input stage. The output stage receives the first enable signal and the first clock signal and generates a clock gating signal according to the first enable signal and the first clock signal. The input stage operates based on a first voltage threshold, and the output stage operates based on a second voltage threshold. The first voltage threshold is different from the second voltage threshold.

Abstract: A semiconductor device includes a plurality of cell rows, a first functional block and a second functional block. The plurality of cell rows at least includes a first cell row and a second cell row. The first functional block is formed in the first cell row and configured to provide a first predetermined function. The second functional block is formed in the second cell row and configured to provide a second predetermined function which is the same as the first predetermined function. The first cell row and the second cell row have at least one different physical property.

Abstract: A semiconductor structure is provided. A logic cell includes a first transistor in a first active region, a second gate electrode and a third gate electrode on opposite sides of the first transistor, a second transistor in a second active region, and a first isolation structure and a second isolation structure on opposite edges of the second active region. The first transistor includes a first gate electrode extending in a first direction. The second and third gate electrodes extend in the first direction, and the first and second isolation structures extend in the first direction. The second transistor and the first transistor share the first gate electrode. The first isolation structure is aligned with the second gate structure in the first direction, and the second isolation structure is aligned with the third gate structure in the first direction.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a cell array having a plurality of rows. The cell array includes a plurality of first logic cells arranged in at least one first row, and a plurality of second logic cells arranged in at least one second row. The first logic cells share a first active region. Each of the second logic cells has a second active region, and the second active regions of two adjacent second logic cells are separated from each other by an isolation structure. The first logic cells of the first row are in contact with the second logic cells of the second row.

Abstract: Semiconductor structures are provided. A semiconductor structure includes a cell array. The cell array includes a first regular cell, a second regular cell and a first mixed cell. Each P-type transistor has a first threshold voltage and each N-type transistor has a second threshold voltage in the first regular cell. Each P-type transistor has a third threshold voltage and each N-type transistor has a fourth threshold voltage in the second regular cell. Each P-type transistor has the first threshold voltage and each N-type transistor has the fourth threshold voltage in the first mixed cell. The first regular cell, the second regular cell and the first mixed cell are arranged in the same row of the cell array. The first mixed cell is arranged between the first and second regular cells and is in contact with the first regular cell.

Abstract: A semiconductor structure is provided. A logic cell with a logic function includes a plurality of first transistors in an active region over a semiconductor substrate, a second transistor in the active region, a third transistor in the active region, and first and second isolation structures on opposite edges of the active region and extending along the first direction. Each first transistor includes a first gate electrode extending along the first direction. The second transistor includes a second gate electrode extending along the first direction. The third transistor includes a third gate electrode extending along the first direction. The first gate electrodes are disposed between the first and second isolation structures. The second gate electrode is disposed between the first gate electrodes and the first isolation structure. The third gate electrode is disposed between the first gate electrodes and the second isolation structure.

Abstract: A multi-bit flip-flop (MBFF) has flip-flops connected to form an internal scan chain. One of the flip-flops outputs a first data-out signal at a first data output terminal of the MBFF, and includes a selection circuit, a latch-based circuit, and a data-out stage circuit. The selection circuit transmits a data signal or a test signal to an output node of the selection circuit to serve as an input signal. The latch-based circuit generates a first signal according to the input signal. The data-out stage circuit receives the first signal, and generates the data-out signal according to the first signal. When the MBFF operates in a test mode, the selection circuit transmits the test signal to serve as the input signal, and the data-out stage circuit keeps the data-out signal at a fixed voltage level regardless of a voltage level of the test signal.

Abstract: A standard cell circuit includes a standard cell unit and a first resistive device. The standard cell unit is coupled to at least one resistor. The first resistive device is coupled to the standard cell unit and provides a first current path for a first current to flow through.

Abstract: A standard cell circuit includes a standard cell unit and a first resistive device. The standard cell unit is coupled to at least one resistor. The first resistive device is coupled to the standard cell unit and provides a first current path for a first current to flow through.

Abstract: A scan test circuit includes: a pulse generator, for generating differential pulses according to a system clock signal; a functional path, including: a D-type latch clocked by the differential pulses; a test path, including: a scan latch clocked by a test clock signal; and a tri-state inverter. When a test enable signal is enabled, the generation of the differential pulses is disabled.

Abstract: A pulse latch includes a pulse generator and a latch circuit. The pulse generator generates first and second pulse signals. The first pulse signal is generated when a test enable signal is in a first state, and the second pulse signal is generated when the test enable signal is in a second state. The latch circuit outputs the latched signal by selectively latching a normal data input signal or a test data input signal. The latch circuit includes first and second tri-state elements. The first tri-state element is controlled by the first pulse signal to enable the test data input signal to be latched when the test enable signal is in the first state. The second tri-state element is controlled by the second pulse signal to enable the normal data input signal to be latched when the test enable signal is in the second state.

Abstract: A scan test circuit includes: a pulse generator, for generating differential pulses according to a system clock signal; a functional path, including: a D-type latch clocked by the differential pulses; a test path, including: a scan latch clocked by a test clock signal; and a tri-state inverter. When a test enable signal is enabled, the generation of the differential pulses is disabled.

Abstract: A scan test circuit includes: a functional path, including: a D-type latch, for receiving an input and generating an output, the D-type latch including a feedback node; and a test path, including: a scan latch, for receiving a test input and generating an output. The scan test circuit also includes a tri-state inverter. The output of the test path is input to the feedback node of the D-type latch and also input to the tri-state inverter. The functional path is clocked by pulses generated by a pulse generator according to a system clock. The test path is clocked by a test clock generated according to a test enable signal and the system clock. When the test enable signal is enabled, the generation of the pulses is disabled.

Abstract: A pulse latch includes a pulse generator and a latch circuit. The pulse generator generates first and second pulse signals. The first pulse signal is generated when a test enable signal is in a first state, and the second pulse signal is generated when the test enable signal is in a second state. The latch circuit outputs the latched signal by selectively latching a normal data input signal or a test data input signal. The latch circuit includes first and second tri-state elements. The first tri-state element is controlled by the first pulse signal to enable the test data input signal to be latched when the test enable signal is in the first state. The second tri-state element is controlled by the second pulse signal to enable the normal data input signal to be latched when the test enable signal is in the second state.

Abstract: A scan test circuit includes: a functional path, including: a D-type latch, for receiving an input and generating an output, the D-type latch including a feedback node; and a test path, including: a scan latch, for receiving a test input and generating an output. The scan test circuit also includes a tri-state inverter. The output of the test path is input to the feedback node of the D-type latch and also input to the tri-state inverter. The functional path is clocked by pulses generated by a pulse generator according to a system clock. The test path is clocked by a test clock generated according to a test enable signal and the system clock. When the test enable signal is enabled, the generation of the pulses is disabled.