Abstract: A lock detection circuit (112) includes a first sampler (113) which samples an input signal (102) at a rate of an output signal (109) to provide a sampled input signal. A second sampler (114) which samples a feedback signal (111) at the rate of the output signal (109) to provide a sampled feedback signal. The sampled input signal is subsequently sampled by a third sampler (115) at the rate of the feedback signal. The sampled feedback signal is subsequently sampled by a fourth sampler (116) at the rate of the input signal. The second sampled input signal and the second sampled feedback signal are subsequently compared (117) and when they substantially match, an indication (122) is set to indicate that phase and/or frequency lock has been obtained.

Abstract: A multibit shifting apparatus (50) of a data processor (40) includes a multiplier (55) such as a modified Booth's recoded multiplier for use in normal multiplication operations. The multibit shifting apparatus (50) also uses the multiplier (55) to perform programmable left and right shifts in order to save circuit area. During a shift operation, a remapping circuit (54) receives a shift count, and remaps the shift count according to a shift direction to provide a remapped signal. The multiplier (55) receives both a shift operand and the remapped signal at inputs thereof. The multiplier (55) provides a first shift result at its output. In one embodiment, an output shifter (57) shifts the first shift result by a fixed amount selectively according to the shift direction to provide a second shift result. The second shift result includes outputs of both left and right shifts in common bit positions.

Abstract: A combined multiplier/shifter (150) uses an existing high-speed multiplier to perform both multiplies and programmable left and right shifts without a dedicated high-speed shifter. A shift decoder (160) used in a shift mode provides first recoded signals according to a shift count and a shift direction. A recoder (161) recodes a multiplier input in a multiply mode to provide second recoded signals. A multiplier array (163) receives either a multiplicand or a shift operand at its multiplicand input, and uses either the first or second recoded signals selectively according to the mode. An output of the multiplier array (163) is either a product in the multiply mode or a first shift result in the shift mode. An output shifter (157) selectively adjusts the first shift result according to the shift direction to provide a second, final shift result.

Abstract: An integrated circuit (40) has a low-power mode in which at least one switched inverter stage (60) of a clock amplifier (41) is disabled in response to a stop signal. The stop signal indicates that the integrated circuit (40) is in low-power mode. In one embodiment, each switched inverter stage is a complementary metal-oxide-semiconductor (CMOS) switched inverter (60), in which an additional P-channel transistor (61) is connected between the source of an inverter P-channel transistor (62) and a positive power supply voltage terminal, and in which an additional N-channel transistor (64) is connected between a source of an inverter N-channel transistor (63) and a negative power supply voltage terminal. A non-switched inverter stage (52) remains active during low-power mode to maintain a DC value of a clock input signal near a switchpoint of the clock amplifier (41).

Abstract: A data processor (10) having an instruction fetch unit (12), a decode and control unit (14), and an execution unit 16 performs conditionally executed instructions in hardware. A conditional break instruction, BRKcc, is inserted within a looping instruction to conditionally terminate the looping instruction with a minimum number of instruction cycles. A conditional do-loop instruction, DO#0, prevents the data processor (10) from executing a do-loop with a loop count within a loop counter (24) of zero upon entry. A conditional repeat instruction, REP#0, prevents a repeat instruction from being executed if a loop count is zero upon entry. A conditional repeat instruction, REPcc, allows a subsequent instruction to be conditionally terminated during execution.

Abstract: A data processing system (10) has programmable normal and low voltage modes of operation. The normal voltage mode of operation enables precharge transistors (32, 34) to couple a voltage of (V.sub.DD -V.sub.tn) to each of a plurality of precharge circuit nodes, such as precharge bus (30), within data processing system (10). During the low voltage mode of operation, the full V.sub.DD is coupled to each precharge circuit node, wherein the power supply voltage during the low voltage mode of operation is reduced. Data processing system (10) has a voltage mode bit (36) for receiving voltage mode information from a source external to data processing system (10). In response to an active logic state within voltage mode bit (36), a low voltage mode clocking circuit (42) is enabled.