Patents by Inventor Kin-Leong Pey
Kin-Leong Pey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10381360Abstract: A method of forming a uniform WL over the MCEL region and resulting device are provided. Embodiments include providing a substrate having a MCEL region, a HV region and a logic region, separated by an isolation region; forming a plurality of CG stacks over the MCEL region, and a plurality of CG dummy stacks over the HV region and the logic region, respectively; forming first and second overlying polysilicon layers with a spacer therebetween, an EG and a WL on the MCEL region formed; planarizing the second polysilicon layer down to upper surface of the plurality of CG stacks and the plurality of CG dummy stacks; and removing portions of the second polysilicon layer in-between the plurality of CG stacks and around the plurality of CG dummy stacks.Type: GrantFiled: March 22, 2018Date of Patent: August 13, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Laiqiang Luo, Sen Mei, Fangxin Deng, Zhiqiang Teo, Fan Zhang, Pinghui Li, Haiqing Zhou, Xingyu Chen, Kin Leong Pey
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Publication number: 20160233157Abstract: A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.Type: ApplicationFiled: April 18, 2016Publication date: August 11, 2016Inventors: Yeow Kheng LIM, Alex SEE, Tae Jong LEE, David VIGAR, Liang Choo HSIA, Kin Leong PEY
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Patent number: 9318378Abstract: A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.Type: GrantFiled: August 21, 2004Date of Patent: April 19, 2016Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Yeow Kheng Lim, Alex See, Tae Jong Lee, David Vigar, Liang Choo Hsia, Kin Leong Pey
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Patent number: 9024286Abstract: Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode.Type: GrantFiled: November 22, 2013Date of Patent: May 5, 2015Assignees: GLOBALFOUNDRIES Singapore PTE Ltd, Nanyang Technological UniversityInventors: Wenhu Liu, Kin-Leong Pey, Nagarajan Raghavan, Chee Mang Ng
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Patent number: 8922003Abstract: A method for forming a device is disclosed. A substrate with a contact region is provided. Vacancy defects are formed in the substrate. The vacancy defects have a peak concentration at a depth DV. A metal based contact is formed in the contact region. The metal based contact has a depth DC which is equal to about DV. The vacancy defects lower the resistance of the metal based contact with the substrate.Type: GrantFiled: January 19, 2012Date of Patent: December 30, 2014Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., Nanyang Technological UniversityInventors: Dexter Xueming Tan, Yoke King Chin, Kin Leong Pey
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Publication number: 20140077148Abstract: Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode.Type: ApplicationFiled: November 22, 2013Publication date: March 20, 2014Applicants: Nanyang Technological University, Globalfoundries Singapore PTE LtdInventors: Wenhu Liu, Kin-Leong Pey, Nagarajan Raghavan, Chee Mang Ng
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Publication number: 20130187264Abstract: A method for forming a device is disclosed. A substrate with a contact region is provided. Vacancy defects are formed in the substrate. The vacancy defects have a peak concentration at a depth DV. A metal based contact is formed in the contact region. The metal based contact has a depth DC which is equal to about DV. The vacancy defects lower the resistance of the metal based contact with the substrate.Type: ApplicationFiled: January 19, 2012Publication date: July 25, 2013Applicants: NANYANG TECHNOLOGICAL UNIVERSITY, GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Dexter Xueming TAN, Yoke King CHIN, Kin Leong PEY
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Patent number: 8338280Abstract: Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire.Type: GrantFiled: July 8, 2010Date of Patent: December 25, 2012Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., Nanyang Technological UniversityInventors: Dexter Tan, Kin Leong Pey, Sai Hooi Yeong, Yoke King Chin, Kuang Kian Ong, Chee Mang Ng
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Publication number: 20120241710Abstract: Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode.Type: ApplicationFiled: March 21, 2011Publication date: September 27, 2012Applicants: NANYANG TECHNOLOGICAL UNIVERSITY, GLOBALFOUNDRIES SINGAPORE PTE LTDInventors: Wenhu Liu, Kin-Leong Pey, Nagarajan Raghavan, Chee Mang Ng
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Patent number: 8101487Abstract: A method for fabricating a semiconductor device is presented. The method includes providing a substrate and forming a gate stack over the substrate. A first laser processing to form vacancy rich regions within the substrate on opposing sides of the gate stack is performed. The vacancy rich regions have a first depth from a surface of the substrate. A first implant causing end of range defect regions to be formed on opposing sides of the gate stack at a second depth from the surface of the substrate is also carried out, wherein the first depth is proximate to the second depth.Type: GrantFiled: May 15, 2009Date of Patent: January 24, 2012Assignees: Nanyang Technological University, National University of Singapore, GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Dexter Xueming Tan, Benjamin Colombeau, Clark Kuang Kian Ong, Sai Hooi Yeong, Chee Mang Ng, Kin Leong Pey
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Publication number: 20120009749Abstract: Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire.Type: ApplicationFiled: July 8, 2010Publication date: January 12, 2012Applicants: NANYANG TECHNOLOGICAL UNIVERSITY, GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Dexter TAN, Kin Leong PEY, Sai Hooi YEONG, Yoke King CHIN, Kuang Kian ONG, Chee Mang NG
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Patent number: 7892905Abstract: A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.Type: GrantFiled: August 2, 2005Date of Patent: February 22, 2011Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Kuang Kian Ong, Kin Leong Pey, King Jien Chui, Ganesh Samudra, Yee Chia Yeo, Yung Fu Chong
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Patent number: 7888224Abstract: A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.Type: GrantFiled: November 14, 2008Date of Patent: February 15, 2011Assignees: Nanyang Technological University, Chartered Semiconductor Manufacturing Ltd., National University Of SingaporeInventors: Kuang Kian Ong, Sai Hooi Yeong, Kin Leong Pey, Lap Chan, Yung Fu Chong
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Publication number: 20100124809Abstract: A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.Type: ApplicationFiled: November 14, 2008Publication date: May 20, 2010Inventors: Kuang Kian Ong, Sai Hooi Yeong, Kin Leong Pey, Lap Chan, Yung Fu Chong
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Publication number: 20090286373Abstract: A method for fabricating a semiconductor device is presented. The method includes providing a substrate and forming a gate stack over the substrate. A first laser processing to form vacancy rich regions within the substrate on opposing sides of the gate stack is performed. The vacancy rich regions have a first depth from a surface of the substrate. A first implant causing end of range defect regions to be formed on opposing sides of the gate stack at a second depth from the surface of the substrate is also carried out, wherein the first depth is proximate to the second depth.Type: ApplicationFiled: May 15, 2009Publication date: November 19, 2009Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD., NANYANG TECHNOLOGICAL UNIVERSITY, NATIONAL UNIVERSITY OF SINGAPOREInventors: Dexter Xueming TAN, Benjamin COLOMBEAU, Clark Kuang Kian ONG, Sai Hooi YEONG, Chee Mang NG, Kin Leong PEY
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Patent number: 7253097Abstract: An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.Type: GrantFiled: June 30, 2005Date of Patent: August 7, 2007Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Yeow Kheng Lim, Chim Seng Seet, Tae Jong Lee, Liang-Choo Hsia, Kin Leong Pey
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Publication number: 20070001303Abstract: An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Yeow Kheng Lim, Chim Seng Seet, Tae Jong Lee, Liang-Choo Hsia, Kin Leong Pey
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Patent number: 7030451Abstract: A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature.Type: GrantFiled: March 15, 2005Date of Patent: April 18, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Pooi See Lee, Kin Leong Pey, Alex See, Lap Chan
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Patent number: 7005716Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.Type: GrantFiled: May 25, 2004Date of Patent: February 28, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Wenhe Lin, Mei-Sheng Zhou, Kin Leong Pey, Simon Chooi
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Patent number: 6891233Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.Type: GrantFiled: December 16, 2003Date of Patent: May 10, 2005Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Wenhe Lin, Mei-Sheng Zhou, Kin Leong Pey, Simon Chooi