Patents by Inventor Kin Li
Kin Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9281236Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs.Type: GrantFiled: May 21, 2015Date of Patent: March 8, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20160049339Abstract: A method of reducing etch time needed for patterning an organic planarization layer (OPL) in a block mask stack so as to minimize damages to gate structures and fin structures in a block mask patterning process is provided. The block mask stack including an OPL, a developable antireflective coating (DARC) layer atop the OPL and a photoresist layer atop the DARC layer is employed to mask one conductivity type of FinFET while exposing the other conductivity type FinFET during source/drain ion implantation. The OPL is configured to have a minimum thickness sufficient to fill in spaces between semiconductor fins and to cover the semiconductor fins. The DARC layer is configured to planarize topography of semiconductor fins so as to provide a planar top surface for the ensuing lithography and etch processes.Type: ApplicationFiled: August 14, 2014Publication date: February 18, 2016Inventor: Wai-kin Li
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Patent number: 9240376Abstract: A method including forming a first via opening in a substrate, the first via opening is self-aligned to a first trench in the substrate, forming a second via opening in the substrate, the second via opening is self-aligned to a second trench in the substrate, a portion of the second via opening overlaps a portion of the first via opening to form an overlap region, and the overlap region having a width (w) equal to or greater than a space (s) between the first trench and the second trench, and removing a portion of the substrate in the overlap region to form a bridge opening, the bridge opening is adjacent to the first and second via openings and extends between the first and second trenches.Type: GrantFiled: August 16, 2013Date of Patent: January 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Junjing Bao, Samuel S. Choi, Wai-Kin Li
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Patent number: 9236575Abstract: After forming a plurality of metal anchors arranged in a matrix of rows and columns and a plurality trenches separating adjacent rows of metal anchors on a substrate, a dispersion comprising charged single-wall carbon nanotubes (SWCNTs) having a surface binding group on each end of the charged SWCNTs is directed to flow through the plurality of trenches. During the flow process, one end of each of the charged SWCNTs binds to a corresponding metal anchor through a surface binding group. An electric field is then applied to align the charged SWCNTs parallel to lengthwise directions of the plurality of trenches such that another end of the each of the SWCNTs binds to an adjacent metal anchor through another surface binding group. The aligned charged SWCNTs can be used as conducting channels for field effect transistors (FETs).Type: GrantFiled: September 5, 2014Date of Patent: January 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Wai-Kin Li, Hanfei Wang
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Publication number: 20150371904Abstract: After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is recessed such that uppermost surfaces of remaining portions of the OPL are located below an uppermost surface of the gate structure but above top surfaces of the semiconductor fins. The remaining portions of the OPL are patterned to expose semiconductor fins in a pFinFET region for subsequent ion implantation. Portions of the OPL that remain on the semiconductor fins in an nFinFET region act as an implantation mask to shield the semiconductor fins in the nFinFET region from the ion implantation.Type: ApplicationFiled: August 28, 2015Publication date: December 24, 2015Inventors: Huihang Dong, Wai-Kin Li
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Publication number: 20150348899Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.Type: ApplicationFiled: August 13, 2015Publication date: December 3, 2015Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20150340292Abstract: After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is recessed such that uppermost surfaces of remaining portions of the OPL are located below an uppermost surface of the gate structure but above top surfaces of the semiconductor fins. The remaining portions of the OPL are patterned to expose semiconductor fins in a pFinFET region for subsequent ion implantation. Portions of the OPL that remain on the semiconductor fins in an nFinFET region act as an implantation mask to shield the semiconductor fins in the nFinFET region from the ion implantation.Type: ApplicationFiled: May 20, 2014Publication date: November 26, 2015Applicant: International Business Machines CorporationInventors: Huihang Dong, Wai-Kin Li
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Patent number: 9190360Abstract: An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.Type: GrantFiled: February 17, 2014Date of Patent: November 17, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Patent number: 9189654Abstract: A set of physical unclonable function (PUF) cells is configured with a set of capacitive devices in an integrated circuit (IC). A subset of PUF cells includes a corresponding subset of capacitive devices that have failed during fabrication. A charging current sufficient to charge an operational capacitive device in a PUF cell is sent to the set of PUF cells. A determination is made whether an output voltage of a PUF cell exceeds a threshold. When the output voltage exceeding the threshold, a logic value of 1 is produced at a position in a bit-string. The determination and the producing is repeated for each PUF cell in the set to output a bit-string, which includes 1s and 0s in random positions. The bit-string is used in a security application as a random stable value owing to a random pattern of 1s and 0s present in the bit-string.Type: GrantFiled: December 4, 2013Date of Patent: November 17, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai Di Feng, Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
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Patent number: 9166588Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and a well formed in the semiconductor substrate. The well includes a first region having a first concentration of ions, and at least one second region having a second concentration that is less than the first concentration. First and second FETs are formed on the well. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.Type: GrantFiled: January 20, 2014Date of Patent: October 20, 2015Assignee: GLOBALFOUNDIRES INC.Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian J. Yang
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Publication number: 20150255326Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs.Type: ApplicationFiled: May 21, 2015Publication date: September 10, 2015Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Patent number: 9117824Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs.Type: GrantFiled: September 20, 2013Date of Patent: August 25, 2015Assignee: International Business Machines CorporationInventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20150235964Abstract: An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.Type: ApplicationFiled: February 17, 2014Publication date: August 20, 2015Applicant: International Business Machines CorporationInventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20150235951Abstract: A combination of gases including at least a fluorocarbon gas, oxygen, and an inert sputter gas is employed to etch at least one opening into an organic photoresist. The amount of oxygen is controlled to a level that limits conversion of a metallic nitride material in an underlying hard mask layer to a metal oxide, and causes organic polymers generated from the organic photoresist to cover peripheral regions of each opening formed in the organic photoresist. The hard mask layer is etched with a taper by the oxygen-limited fluorine-based etch chemistry provided by the combination of gases. The taper angle can be controlled such that a shrink ratio of the lateral dimension by the etch can exceed 2.0.Type: ApplicationFiled: May 1, 2015Publication date: August 20, 2015Inventors: Samuel S. Choi, Wai-kin Li
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Publication number: 20150228578Abstract: An electronic fuse structure including an Mx level having a first Mx metal, and a second Mx metal, and an Mx+1 level having a first Mx+1 metal, a second Mx+1 metal, a first via, a second via, and a conductive path extending from the first via to the second via and partially encircling the first via, the first via extending vertically and electrically connecting the first Mx metal to the first Mx+1 metal, and the second via extending vertically and electrically connecting the second Mx metal to the second Mx+1 metal.Type: ApplicationFiled: April 24, 2015Publication date: August 13, 2015Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Wai-Kin Li, Naftali E. Lustig, Andrew H. Simon
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Patent number: 9105638Abstract: In an embodiment of the present invention, a semiconductor device comprises a non-fuse area that has a non-fuse via, a non-fuse line, and a non-fuse dielectric stack. The semiconductor device further comprises a fuse area that has a fuse via, a fuse line, and a fuse dielectric stack. The fuse dielectric stack comprises at least a first dielectric and a second dielectric material. The fuse via is at least partially embedded in the first dielectric material and the fuse line is embedded in the second dielectric material.Type: GrantFiled: November 11, 2013Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Wai-Kin Li, Naftali E. Lustig, Andrew H. Simon
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Patent number: 9105641Abstract: The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.Type: GrantFiled: September 15, 2014Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Samuel S. Choi, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Wai-Kin Li, Christopher J. Penny, Shom Ponoth, Chih-Chao Yang, Yunpeng Yin
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Patent number: 9093387Abstract: A stack of a dielectric material layer and a metallic material layer are formed on a substrate. A first organic planarization layer, a non-metallic hard mask layer, and a photoresist layer are sequentially deposited over the metallic material layer. The photoresist layer is lithographically patterned, and the pattern in the photoresist layer is transferred through the non-metallic hard mask layer, the first organic planarization layer, and the metallic material layer to form a cavity. A second organic planarization layer is deposited within the cavity and over remaining portions of the photoresist layer. The second organic planarization layer and the photoresist layer are recessed, and the non-metallic hard mask layer is subsequently removed. Remaining portions of the first and second organic planarization layers are simultaneously removed to provide physically exposed surfaces of the patterned metallic material layer and a top surface of the dielectric material layer.Type: GrantFiled: January 8, 2014Date of Patent: July 28, 2015Assignee: International Business Machines CorporationInventors: Scott D. Allen, Kuang-Jung Chen, Huihang Dong, Wai-Kin Li
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Patent number: 9093452Abstract: A method of forming an electronic fuse including forming an Mx level including a first and a second Mx metal, forming a first Mx+1 dielectric above the Mx level, forming a conductive path on a portion of the first Mx+1 dielectric, forming a second Mx+1 dielectric above the first Mx+1 dielectric and above the conductive path, the first and second Mx+1 dielectrics together form an Mx+1 level, forming a first and a second via in the Mx+1 level, the conductive path extending from the first via to the second via and partially encircling the first via, and forming a first and second Mx+1 metal in the Mx+1 level, the first via extending vertically and electrically connecting the first Mx metal to the first Mx+1 metal, and the second via extending vertically and electrically connecting the second Mx metal to the second Mx+1 metal.Type: GrantFiled: March 8, 2013Date of Patent: July 28, 2015Assignee: International Business Machines CorporationInventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Wai-Kin Li, Naftali E. Lustig, Andrew H. Simon
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Publication number: 20150207505Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and a well formed in the semiconductor substrate. The well includes a first region having a first concentration of ions, and at least one second region having a second concentration that is less than the first concentration. First and second FETs are formed on the well. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.Type: ApplicationFiled: January 20, 2014Publication date: July 23, 2015Applicant: International Business Machines CorporationInventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian J. Yang