Patents by Inventor Kin Man Ng
Kin Man Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9419748Abstract: A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal.Type: GrantFiled: August 7, 2014Date of Patent: August 16, 2016Assignee: SK Hynix memory solutions Inc.Inventors: Kwok W. Yeung, Kin Man Ng, Kin Ming Chan
-
Patent number: 8984364Abstract: Second interleaved data is de-interleaved using a second interleaving mapping to obtain encoded data. The second interleaved data includes a copy of constrained data in the same sequence and having the same values as the constrained data. Also, the portion of the second interleaved data that includes the copy of the constrained data satisfies a modulation constraint associated with limiting a number of consecutive events to a maximum number of consecutive events. The encoded data is decoded to obtain first interleaved data and the first interleaved data is de-interleaved using a first interleaving mapping to obtain the constrained data, a copy of which is included in the second interleaved data, where the constrained data satisfies the modulation constraint.Type: GrantFiled: October 14, 2013Date of Patent: March 17, 2015Assignee: SK Hynix Memory Solutions Inc.Inventors: Lingqi Zeng, Yu Kou, Kin Man Ng
-
Publication number: 20150033093Abstract: A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal.Type: ApplicationFiled: August 7, 2014Publication date: January 29, 2015Inventors: Kwok W. Yeung, Kin Man Ng, Kin Ming Chan
-
Patent number: 8918696Abstract: A method for decoding data is disclosed. The method includes partitioning a low-density parity check (LDPC) matrix into a plurality of groups, each comprising one or more check node layers. The method further includes selecting one of the groups based at least in part on a cost function, the cost function based at least in part on information associated with a variable node, or information associated with a check node, or both. The method further includes performing LDPC layered decoding on the selected group.Type: GrantFiled: April 11, 2011Date of Patent: December 23, 2014Assignee: SK hynix memory solutions inc.Inventors: Kin Man Ng, Kwok W. Yeung, Lingqi Zeng, Yu Kou, Aditi R. Ganesan
-
Patent number: 8839051Abstract: A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal.Type: GrantFiled: February 24, 2012Date of Patent: September 16, 2014Assignee: SK hynix memory solutions inc.Inventors: Kwok W. Yeung, Kin Man Ng, Kin Ming Chan
-
Publication number: 20140122965Abstract: Second interleaved data is de-interleaved using a second interleaving mapping to obtain encoded data. The second interleaved data includes a copy of constrained data in the same sequence and having the same values as the constrained data. Also, the portion of the second interleaved data that includes the copy of the constrained data satisfies a modulation constraint associated with limiting a number of consecutive events to a maximum number of consecutive events. The encoded data is decoded to obtain first interleaved data and the first interleaved data is de-interleaved using a first interleaving mapping to obtain the constrained data, a copy of which is included in the second interleaved data, where the constrained data satisfies the modulation constraint.Type: ApplicationFiled: October 14, 2013Publication date: May 1, 2014Applicant: SK Hynix Memory Solutions Inc.Inventors: Lingqi Zeng, Yu Kou, Kin Man Ng
-
Patent number: 8659847Abstract: User level data associated with a location adjacent to a desired location on a magnetic disk storage is received. Media level data associated with the adjacent location is generated based at least in part on the user level data associated with the adjacent location; a processor which is configured to generate the media level data associated with the adjacent location is a same processor which is configured to generate media level data based at least in part on user level data during a write process. The media level data associated with the adjacent location is used to remove inter-track interference (ITI) associated with the adjacent location from a signal read back from the desired location.Type: GrantFiled: February 7, 2012Date of Patent: February 25, 2014Assignee: SK hynix memory solutions inc.Inventors: Kwok W. Yeung, Kin Man Ng, Kin Ming Chan
-
Patent number: 8650453Abstract: A cost function is obtained. For each of a plurality of groups of nodes, the cost function is evaluated by obtaining, for a given group of nodes, one or more reliability values associated with the given group of nodes; the one or more reliability values include sign and magnitude. For a given group of nodes, a reliability value with a smallest magnitude is selected where the evaluated cost function for the given group of nodes is set to the smallest magnitude. One of the plurality of groups of nodes is selected based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of nodes.Type: GrantFiled: February 28, 2013Date of Patent: February 11, 2014Assignee: SK hynix memory solutions inc.Inventors: Kin Man Ng, Lingqi Zeng, Yu Kou, Kwok W. Yeung
-
Patent number: 8583979Abstract: A technique for processing data. The technique includes modulation encoding input data. A first interleaving process is used to obtain first interleaved data. The first interleaved data is systematically encoded. The systematically encoded data is interleaved using a second interleaving process to obtain second interleaved data. The second interleaving process is an inverse of the first interleaving process, at least for a common portion.Type: GrantFiled: May 19, 2009Date of Patent: November 12, 2013Assignee: SK hynix memory solutions inc.Inventors: Lingqi Zeng, Yu Kou, Kin Man Ng
-
Patent number: 8572471Abstract: Decoding is performed on input data to obtain first decoded data using a first error correction decoder. If decoding by a second error correction decoder on the first decoded data fails, decoding is performed using an output of the second decoder and using the first decoder. A reservation request is sent from the second error correction decoder to a memory prior to completion of the decoding on the first decoded data. Space is reserved in the memory in response to receiving the reservation request from the second decoder.Type: GrantFiled: October 19, 2012Date of Patent: October 29, 2013Assignee: SK hynix memory solutions inc.Inventors: Kwok W. Yeung, Kin Man Ng
-
Patent number: 8572463Abstract: In processing quasi-cyclic low-density parity-check (QC-LDPC) data, an input signal is received which includes decision and reliability information corresponding to unpadded data. Decision and reliability information corresponding to padded data is introduced into the input signal. Message passing is performed one or more times to obtain decoded data. This includes using (1) the decision and reliability information corresponding to the unpadded data and (2) the decision and reliability information corresponding to the padded data, where a preference is given to the decision and reliability information corresponding to the unpadded data over the decision and reliability information corresponding to the unpadded data during message passing. Zero padding is removed from the decoded data.Type: GrantFiled: February 25, 2011Date of Patent: October 29, 2013Assignee: SK hynix memory solutions inc.Inventors: Lingqi Zeng, Yu Kou, Kin Man Ng, Kwok W. Yeung
-
Publication number: 20130246880Abstract: A cost function is obtained. For each of a plurality of groups of nodes, the cost function is evaluated by obtaining, for a given group of nodes, one or more reliability values associated with the given group of nodes; the one or more reliability values include sign and magnitude. For a given group of nodes, a reliability value with a smallest magnitude is selected where the evaluated cost function for the given group of nodes is set to the smallest magnitude. One of the plurality of groups of nodes is selected based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of nodes.Type: ApplicationFiled: February 28, 2013Publication date: September 19, 2013Applicant: SK HYNIX MEMORY SOLUTIONS INC.Inventors: Kin Man Ng, Lingqi Zeng, Yu Kou, Kwok W. Yeung
-
Patent number: 8504894Abstract: Encoding is performed by putting a low-density parity-check (LDPC) generator matrix into partial quasi-cyclic form comprising an identity matrix, a parity generator matrix, a zero matrix and a remainder matrix. The parity generator matrix is quasi-cyclic and the remainder matrix is not quasi-cyclic. An encoder is used to generate LDPC encoded data using the parity generator matrix and without using the remainder matrix.Type: GrantFiled: March 2, 2011Date of Patent: August 6, 2013Assignee: SK hynix memory solutions inc.Inventors: Lingqi Zeng, Yu Kou, Kin Man Ng, Kwok W. Yeung
-
Patent number: 8489971Abstract: A system for adapting coefficients of a soft output Viterbi algorithm (SOVA) is disclosed. The system includes a receiver configured to select an output of an SOVA detector at least in part based on a criterion. The receiver is configured to store the selected output of the SOVA detector. The receiver is further configured to store a signal that corresponds to the stored selected output of the SOVA detector, wherein the input to the SOVA detector is derived from the signal. The receiver is further configured to adapt a plurality of coefficients of the SOVA detector at least in part based on the stored selected output of the SOVA detector, the stored signal, and a corresponding data pattern. The system includes an interface coupled to the receiver and configured to receive samples.Type: GrantFiled: May 27, 2011Date of Patent: July 16, 2013Assignee: SK hynix memory solutions inc.Inventors: Kai Keung Chan, Kin Man Ng, Xin-Ning Song, Jason Bellorado
-
Patent number: 8484539Abstract: An iterative error correction coding (ECC) decoder is configured to operate in a first higher-power and higher-performance operating mode. At least some part of a system that includes the iterative ECC decoder is monitored. It is determining whether to switch the iterative ECC decoder from the first higher-power and higher-performance operating mode to a second lower-power and lower-performance operating mode based at least in part on the monitoring. The iterative ECC decoder is configured to operate in the second lower-power and lower-performance operating mode in the event it is determined to switch operating modes.Type: GrantFiled: May 28, 2010Date of Patent: July 9, 2013Assignee: SK hynix memory solutions inc.Inventors: Kwok W. Yeung, Kin Man Ng
-
Patent number: 8448041Abstract: Low-density parity-check (LDPC) encoding is performed by encoding input data using a first sub-matrix of a parity check matrix to obtain intermediate data. The parity check matrix includes the first sub-matrix and a second sub-matrix having a matrix inversion. The intermediate data is encoded using the matrix inversion of the second sub-matrix of the parity check matrix.Type: GrantFiled: December 16, 2010Date of Patent: May 21, 2013Assignee: SK hynix memory solutions inc.Inventors: Lingqi Zeng, Abhiram Prabhakar, Kin Man Ng, Yu Kou
-
Patent number: 8443257Abstract: Encoding is performed by dividing a quasi-cyclic low-density parity-check (QC-LDPC) parity check matrix into a first sub-matrix and a second sub-matrix. The first sub-matrix includes a plurality of circulant vectors and the plurality of circulant vectors is associated with a circulant size. Input data is received having a length which is a product of an integer multiplier and the circulant size. A first stage of multi-stage LDPC encoding is performed using the input data and a subset of the plurality of circulant vectors; the number of circulant vectors in the subset equals the integer multiplier.Type: GrantFiled: March 2, 2011Date of Patent: May 14, 2013Assignee: SK hynix memory solutions inc.Inventors: Lingqi Zeng, Yu Kou, Kin Man Ng, Kwok W. Yeung
-
Patent number: 8418020Abstract: A cost function is obtained. For each of a plurality of groups of check nodes associated with low-density parity-check (LDPC) encoded data, the cost function is evaluated using information associated with a variable node and/or information associated with a check node. One of the groups of check nodes is selecting based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of check nodes.Type: GrantFiled: June 7, 2012Date of Patent: April 9, 2013Assignee: SK hynix memory solutions inc.Inventors: Kin Man Ng, Lingqi Zeng, Yu Kou, Kwok W. Yeung
-
Patent number: 8321772Abstract: A technique for decoding information, including a Viterbi decoder configured to decode (1) Front-end processed ADC data and (2) an output of an iterative error correction decoder in the event error correction decoding fails. The iterative error correction decoder is configured to decode Viterbi decoded data generated by the Viterbi decoder.Type: GrantFiled: October 14, 2009Date of Patent: November 27, 2012Assignee: Link—A—Media Devices CorporationInventors: Kwok W. Yeung, Kin Man Ng
-
Patent number: 8281224Abstract: Data is processed by obtaining data and redundant information from an expected position in a channel. Soft position information associated with the data is obtained and error correction decoding is performed using the data, the redundant information, and the soft position information to obtain a decoded position and decoded data. It is determined if the decoded position matches the expected position and the decoded data is output in the event the decoded position matches the expected position.Type: GrantFiled: July 24, 2009Date of Patent: October 2, 2012Assignee: Link—A—Media Devices CorporationInventors: Yu Kou, Lingqi Zeng, Kin Man Ng, Kwok W. Yeung