Patents by Inventor Kin P. Cheung
Kin P. Cheung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11507135Abstract: A molecular scrivener reads data from or writes data to a macromolecule and includes: a pair of shielding electrodes; a scrivener electrode between the first and second shielding electrodes and that electrically floats at a third potential that, in an absence of a charged or dipolar moiety of the macromolecule, is intermediate between the first and second potentials and changes in a presence of the charged or dipolar moiety; a dielectric layer interposed between shielding electrodes and the scrivener electrode; and a nanopore that communicates the macromolecule through the electrodes and dielectric layers. Reading data from or writing data to a macromolecule includes: sequentially receiving, at the scrivener electrode, individual moieties of the macromolecule so that the third potential responds to individual moieties; communicating the macromolecule from the scrivener electrode to the second shielding electrode and from second shielding electrode to expel the macromolecule from the nanopore.Type: GrantFiled: April 15, 2019Date of Patent: November 22, 2022Assignee: GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCEInventors: Kin P Cheung, Joseph W Robertson, John J Kasianowicz
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Publication number: 20200326748Abstract: A molecular scrivener reads data from or writes data to a macromolecule and includes: a pair of shielding electrodes; a scrivener electrode between the first and second shielding electrodes and that electrically floats at a third potential that, in an absence of a charged or dipolar moiety of the macromolecule, is intermediate between the first and second potentials and changes in a presence of the charged or dipolar moiety; a dielectric layer interposed between shielding electrodes and the scrivener electrode; and a nanopore that communicates the macromolecule through the electrodes and dielectric layers. Reading data from or writing data to a macromolecule includes: sequentially receiving, at the scrivener electrode, individual moieties of the macromolecule so that the third potential responds to individual moieties; communicating the macromolecule from the scrivener electrode to the second shielding electrode and from second shielding electrode to expel the macromolecule from the nanopore.Type: ApplicationFiled: April 15, 2019Publication date: October 15, 2020Inventors: Kin P Cheung, Joseph W Robertson, John J Kasianowicz
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Patent number: 10247814Abstract: A phase shift detector includes: an interferometer; and a microwave probe in electrical communication with the interferometer, the microwave probe including: a primary shield electrode; and a transmission electrode disposed proximate to the primary shield electrode, the transmission electrode and the primary shield electrode being exposed and arranged to produce an electric field, wherein the transmission electrode is isolated electrically from the primary shield electrode.Type: GrantFiled: January 14, 2016Date of Patent: April 2, 2019Assignee: NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGYInventors: Kin P. Cheung, Jason T. Ryan, Jason Campbell
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Patent number: 10241149Abstract: A massively parallel wafer-level reliability system to test a reliability of wafers includes: a test platform; stations disposed on the test platform, wherein an individual test station receives a wafer and includes: a chuck disposed on the test platform; a probe including contactors that electrically contact the wafer; and a temperature controller to control a temperature of the wafer; a control platform disposed among the test stations; and a system controller to independently control the test stations and that is in electrical communication with the temperature controller, wherein the reliability of the wafers is tested in parallel by the test stations.Type: GrantFiled: September 24, 2016Date of Patent: March 26, 2019Assignee: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCEInventor: Kin P. Cheung
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Publication number: 20170089950Abstract: A massively parallel wafer-level reliability system to test a reliability of wafers includes: a test platform; stations disposed on the test platform, wherein an individual test station receives a wafer and includes: a chuck disposed on the test platform; a probe including contactors that electrically contact the wafer; and a temperature controller to control a temperature of the wafer; a control platform disposed among the test stations; and a system controller to independently control the test stations and that is in electrical communication with the temperature controller, wherein the reliability of the wafers is tested in parallel by the test stations.Type: ApplicationFiled: September 24, 2016Publication date: March 30, 2017Inventor: KIN P. CHEUNG
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Patent number: 9507004Abstract: An electron spin resonance spectrometer includes a bridge to transmit an excitation frequency and to receive a signal frequency; a probe electrically connected to the bridge and comprising: a first conductor in electrical communication with the bridge to transmit the signal frequency to the bridge; a shorting member electrically connected to the first conductor to transmit the excitation frequency to a sample, to produce the signal frequency, and to transmit the signal frequency to the first conductor; and a second conductor electrically connected to the shorting member; and a magnet disposed proximate to the probe.Type: GrantFiled: April 3, 2014Date of Patent: November 29, 2016Assignees: THE GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE, THE PENN STATE RESEARCH FOUNDATIONInventors: Jason P. Campbell, Kin P. Cheung, Jason T Ryan, Patrick M. Lenahan
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Publication number: 20160209275Abstract: A phase shift detector includes: an interferometer; and a microwave probe in electrical communication with the interferometer, the microwave probe including: a primary shield electrode; and a transmission electrode disposed proximate to the primary shield electrode, the transmission electrode and the primary shield electrode being exposed and arranged to produce an electric field, wherein the transmission electrode is isolated electrically from the primary shield electrode.Type: ApplicationFiled: January 14, 2016Publication date: July 21, 2016Inventors: KIN P. CHEUNG, JASON T. RYAN, JASON CAMPBELL
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Publication number: 20140210473Abstract: An electron spin resonance spectrometer includes a bridge to transmit an excitation frequency and to receive a signal frequency; a probe electrically connected to the bridge and comprising: a first conductor in electrical communication with the bridge to transmit the signal frequency to the bridge; a shorting member electrically connected to the first conductor to transmit the excitation frequency to a sample, to produce the signal frequency, and to transmit the signal frequency to the first conductor; and a second conductor electrically connected to the shorting member; and a magnet disposed proximate to the probe.Type: ApplicationFiled: April 3, 2014Publication date: July 31, 2014Applicant: NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGYInventors: JASON P. CAMPBELL, KIN P. CHEUNG, JASON T. RYAN, PATRICK M. LENAHAN
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Patent number: 7548067Abstract: Methods for determining capacitance values of a metal on semiconductor (MOS) structure are provided. A time domain reflectometry circuit may be loaded with a MOS structure. The MOS structure may be biased with various voltages, and reflectometry waveforms from the applied voltage may be collected. The capacitance of the MOS structure may be determined from the reflectometry waveforms.Type: GrantFiled: October 25, 2006Date of Patent: June 16, 2009Assignees: Sematech, Inc., Rutgers UniversityInventors: Kin P. Cheung, Dawei Heh, Byoung Hun Lee, Rino Choi
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Publication number: 20080100283Abstract: Methods for determining capacitance values of a metal on semiconductor (MOS) structure are provided. A time domain reflectometry circuit may be loaded with a MOS structure. The MOS structure may be biased with various voltages, and reflectometry waveforms from the applied voltage may be collected. The capacitance of the MOS structure may be determined from the reflectometry waveforms.Type: ApplicationFiled: October 25, 2006Publication date: May 1, 2008Inventors: Kin P. Cheung, Dawei Heh, Byoung Hun Lee, Rino Choi
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Patent number: 6936494Abstract: A process for hermetically packaging a microscopic structure including a MEMS device is provided. The process for the present invention includes the steps of depositing a capping layer of sacrificial material patterned by lithography over the microscopic structure supported on a substrate, depositing a support layer of a dielectric material patterned by lithography over the capping layer, providing a plurality of vias through the support layer by lithography, removing the capping layer via wet etching to leave the support layer intact in the form of a shell having a cavity occupied by the microscopic structure, depositing a metal layer over the capping layer that is thick enough to provide a barrier against gas permeation, but thin enough to leave the vias open, and selectively applying under high vacuum a laser beam to the metal proximate each via for a sufficient period of time to melt the metal for sealing the via.Type: GrantFiled: October 22, 2003Date of Patent: August 30, 2005Assignee: Rutgers, The State University of New JerseyInventor: Kin P. Cheung
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Publication number: 20040126953Abstract: A process for hermetically packaging a microscopic structure including a MEMS device is provided. The process for the present invention includes the steps of depositing a capping layer of sacrificial material patterned by lithography over the microscopic structure supported on a substrate, depositing a support layer of a dielectric material patterned by lithography over the capping layer, providing a plurality of vias through the support layer by lithography, removing the capping layer via wet etching to leave the support layer intact in the form of a shell having a cavity occupied by the microscopic structure, depositing a metal layer over the capping layer that is thick enough to provide a barrier against gas permeation, but thin enough to leave the vias open, and selectively applying under high vacuum a laser beam to the metal proximate each via for a sufficient period of time to melt the metal for sealing the via.Type: ApplicationFiled: October 22, 2003Publication date: July 1, 2004Inventor: Kin P. Cheung
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Patent number: 6524872Abstract: The invention relates to the measurement and monitoring of plasma-damage, and to the evaluation of the lifetime of integrated circuits under nominal operating conditions. The method calculates the intrinsic, or damage-free, lifetime of a particular transistor device by measuring the change in transconductance as a function of time for a given device over a short period of time. The change in the transconductance as a function of time, i.e., the slope of the degradation curve, is measured and then compared to a reference value. The present invention thus allows the use of hot-carrier stress method to determine plasma damage in a time efficient manner without the need of applying high acceleration voltages.Type: GrantFiled: May 24, 1999Date of Patent: February 25, 2003Assignee: Agere Systems Inc.Inventor: Kin P. Cheung
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Patent number: 6365426Abstract: The present invention provides a method of determining a reliability of a semiconductor device. In an exemplary embodiment, the method determines an oxide stress voltage as a function of an antenna ratio of a semiconductor device, determines an oxide area of the semiconductor device and determines a failure fraction of the semiconductor device as a function of the oxide stress voltage and the oxide area.Type: GrantFiled: April 30, 2000Date of Patent: April 2, 2002Assignee: Agere Systems Guardian CorporationInventors: Kin P. Cheung, Philip W. Mason
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Patent number: 5008217Abstract: Direct contact to shallow junctions in integrated circuits and interconnection between these contacts is achievable by utilizing a specific aluminum CVD process. In this process the aluminum is deposited utilizing a triisobutyl aluminum precursor onto a substrate having a nucleation layer, e.g. a titanium nitride layer. By appropriate choice of this nucleation layer to control the nucleation of the depositing aluminum, suitable contact is made while avoiding void defects present in the absence of such layer.Type: GrantFiled: June 8, 1990Date of Patent: April 16, 1991Assignee: AT&T Bell LaboratoriesInventors: Christopher J. Case, Kin P. Cheung, Ruichen Liu, Ronald J. Schutz, Richard S. Wagner