Patents by Inventor Kin-Shiung Chang

Kin-Shiung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5261157
    Abstract: A process for the assembly of a pin grid array electronic package by vacuum lamination is provided. A vacuum is applied to the package components at the same time the components are bonded with a dielectric sealant. The sealant flow into holes formed in the package base is improved thereby electrically isolating terminal pins which pass through the holes.
    Type: Grant
    Filed: January 22, 1991
    Date of Patent: November 16, 1993
    Assignee: Olin Corporation
    Inventor: Kin-Shiung Chang
  • Patent number: 5144412
    Abstract: A pin grid array package is provided. An array of terminal pins pass through apertures formed in an interconnect tape. The terminal pins are electrically connected to circuit traces formed on interconnect tape. The electrically conductive bond between the terminal pins and circuit traces is either by a mechanical cinch by soldering. In one embodiment, at least a portion of the interconnect tape, terminal pins and a heat sink are embedded in a molding polymer resin.
    Type: Grant
    Filed: August 2, 1990
    Date of Patent: September 1, 1992
    Assignee: Olin Corporation
    Inventors: Kin-Shiung Chang, Thomas A. Armer, William G. Bridges
  • Patent number: 4970781
    Abstract: A process plate for the manufacture of molded electronic packages such as plastic pin grid array packages is provided. The process plate is a single fixture which is used to position terminal pins, align the pins for electrical interconnection and form the base of the mold during encapsulation. In one embodiment, the process plate comprises a support plate which is used for all standard terminal pin configurations and a thin cover plate which is specific for each terminal pin configuration. The process plate reduces the number of fixtures required to mold an electronic package reducing both cost and assembly error.
    Type: Grant
    Filed: August 10, 1989
    Date of Patent: November 20, 1990
    Assignee: Olin Corporation
    Inventors: Kin-Shiung Chang, Thomas A. Armer, Jeffrey S. Braden, George A. Anderson
  • Patent number: 4965227
    Abstract: A process for forming an integrated circuit pin grid array package comprising a flexible metal tape adapted for use in tape automated bonding with a plurality of holes. Terminal pins are inserted in the holes and the tapes and pins are disposed within a mold so that a cavity is formed about the pins and tape. The cavity is filled with a polymer resin so as to at least partially surround and support the pins and tape and thereby form the plastic encapsulated pin grid array.
    Type: Grant
    Filed: February 2, 1988
    Date of Patent: October 23, 1990
    Assignee: Olin Corporation
    Inventors: Kin-Shiung Chang, Thomas A. Armer, William G. Bridges
  • Patent number: 4816426
    Abstract: A process for forming an integral circuit pin grid array package comprising a flexible metal tape adapted for use in tape automated bonding with a plurality of holes. Terminal pins are inserted in the holes and the tape and pins are disposed within a mold so that a cavity is formed about the pins and tape. The cavity is filled with a polymer resin so as to at least partially surround and support the pins and tape and thereby form the plastic encapsulated pin grid array.
    Type: Grant
    Filed: May 21, 1987
    Date of Patent: March 28, 1989
    Assignee: Olin Corporation
    Inventors: William G. Bridges, Thomas A. Armer, Kin-Shiung Chang