Patents by Inventor Kin Sin
Kin Sin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967631Abstract: The present disclosure provides a power semiconductor device and a manufacturing method thereof. In order to provide a power semiconductor device with improved latch-up immunity but without increasing device power loss and costs, a hole current path in a fourth semiconductor region of a first conductivity type between a gate trench and a dummy gate trench is shortened by providing a first contact trench between two adjacent gate trenches, and providing a second contact trench between the gate trench and a dummy gate trench such that the width and depth of the second contact trench are respectively greater than those of the first contact trench. The effect of the hole current on the potential rise of the fourth semiconductor region of the first conductivity type is suppressed, thereby suppressing the latch-up effect, and enhancing the switching reliability.Type: GrantFiled: October 30, 2023Date of Patent: April 23, 2024Assignee: JSAB TECHNOLOGIES (SHENZHEN) LTD.Inventors: Hao Feng, Yong Liu, Jing Deng, Johnny Kin On Sin
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Publication number: 20240079275Abstract: A gate insulating film has a multilayer structure including a SiO2 film, a LaAlO3 film, and an Al2O3 film that are sequentially stacked, relative permittivity of the gate insulating film being optimized by the LaAlO3 film. In forming the LaAlO3 film constituting the gate insulating film, a La2O3 film and an Al2O3 film are alternately deposited repeatedly using an ALD method. The La2O3 film is deposited first, whereby during a POA performed thereafter, a sub-oxide of the surface of the SiO2 film is removed by a cleaning effect of lanthanum atoms in the La2O3 film. A temperature of the POA is suitably set in a range from 700 degrees C. to less than 900 degrees C.Type: ApplicationFiled: April 27, 2023Publication date: March 7, 2024Applicant: FUJI ELECTRIC CO., LTD.Inventors: Takashi TSUJI, Yuichi ONOZAWA, Naoto FUJISHIMA, Linhua HUANG, Johnny Kin On SIN
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Publication number: 20230343827Abstract: Disclosed are a power semiconductor device and a preparation method thereof, which belongs to the field of power semiconductor devices. By introducing a punch-through triode structure for electron extraction in a drift region, the frontside hole injection efficiency is reduced, and hole currents from emitters are converted into electron drift currents without significantly increasing on-state voltage drop. In addition, by changing the density and topography of a frontside trench, the adjustment of punch-through area and position is achieved, which in turn changes the electron extraction and frontside hole injection efficiency. The disclosed method increases the design flexibility and design dimension of the device.Type: ApplicationFiled: January 10, 2023Publication date: October 26, 2023Inventors: Yong LIU, Hao FENG, Johnny Kin On SIN
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Publication number: 20230290890Abstract: An electron extraction type free-wheeling diode device and a preparation method thereof are provided by the present disclosure, and more than one first structures for increasing the density of electron extraction pathways are provided on a N-type drift region. Each of the first structures includes a lightly doped P-type base region, a heavily doped N-type emitter region located on the lightly doped P-type base region, a P-type trench anode region, and a trench region located on the P-type trench anode region. The barrier height of the punch-through NPN triode can be tuned in a wide range, which has beneficial effects on soft and fast adjustment of the reverse recovery process.Type: ApplicationFiled: December 21, 2022Publication date: September 14, 2023Inventors: Hao FENG, Yong LIU, Johnny Kin On SIN
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Patent number: 11127822Abstract: At edge termination region, a trench is disposed near an interface of an active region. Inside the trench, an embedded insulating film is embedded, and inside the embedded insulating film, a FP long in a direction of depth is disposed. The FP curves outwardly away from an inner sidewall of the trench as a depth from a base front surface increases. At least near a bottom end of the FP, a distance between the FP and the inner sidewall of trench is greater than a width of the groove. The FP is connected to a front surface electrode that extends on the embedded insulating film. As a result, breakdown voltage can be enhanced, adverse effects of the surface charge can be reduced, and chip size can be further reduced.Type: GrantFiled: April 25, 2017Date of Patent: September 21, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Wentao Yang, Johnny Kin On Sin, Yuichi Onozawa, Kaname Mitsuzuka
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Patent number: 11081575Abstract: An insulated gate bipolar transistor (IGBT) device and a method for manufacturing the same are provided. The present disclosure relates to power semiconductor devices. In order to relieve the problem of wafer warping caused by trench stress in an IGBT manufacturing process without affecting other performance parameters of the IGBT, it provides the following technical solution: optimizing the design of arrangement densities and arrangement regions of device trenches. The present disclosure can alleviate the problem of wafer warping caused by trench stress in the IGBT manufacturing process, improve the product yield of IGBT chips, and enhance the latch-up immunity of the IGBT, so that the IGBT is more robust and durable.Type: GrantFiled: December 17, 2019Date of Patent: August 3, 2021Assignee: ZHONG SHAN HONSON ELECTRONIC TECHNOLOGIES LIMITEDInventors: Johnny Kin On Sin, Hao Feng, Song Yuan
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Publication number: 20200212208Abstract: An insulated gate bipolar transistor (IGBT) device and a method for manufacturing the same are provided. The present disclosure relates to power semiconductor devices. In order to relieve the problem of wafer warping caused by trench stress in an IGBT manufacturing process without affecting other performance parameters of the IGBT, it provides the following technical solution: optimizing the design of arrangement densities and arrangement regions of device trenches. The present disclosure can alleviate the problem of wafer warping caused by trench stress in the IGBT manufacturing process, improve the product yield of IGBT chips, and enhance the latch-up immunity of the IGBT, so that the IGBT is more robust and durable.Type: ApplicationFiled: December 17, 2019Publication date: July 2, 2020Inventors: Johnny Kin On SIN, HAO FENG, SONG YUAN
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Patent number: 10593767Abstract: A structure and a manufacturing method of a power semiconductor device are provided. A structure of thin semi-insulating field plates (32, 33, 34) located between metal electrodes (21, 22, 23) at the surface of the power semiconductor device is provided. The thin semi-insulating field plates (32, 33, 34) are formed by depositing before metallization and annealing after the metallization. The present invention can be used in lateral power semiconductor devices and vertical power semiconductor devices.Type: GrantFiled: November 26, 2014Date of Patent: March 17, 2020Inventors: Chun Wai Ng, Iftikhar Ahmed, Johnny Kin On Sin
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Patent number: 10249720Abstract: At edge termination region, a trench is disposed near an interface of an active region. Inside the trench, an embedded insulating film is embedded, and inside the embedded insulating film, a FP long in a direction of depth is disposed. The FP curves outwardly away from an inner side wall of the trench as a depth from a base front surface increases. At least near a bottom end of the FP, a distance between the FP and the inner side wall of the trench is greater than a width of the groove. The FP is connected to a front surface electrode that extends on the embedded insulating film. As a result, breakdown voltage may be enhanced, adverse effects of the surface charge may be reduced, and chip size may be further reduced.Type: GrantFiled: March 30, 2017Date of Patent: April 2, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Wentao Yang, Johnny Kin On Sin, Yuichi Onozawa
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Patent number: 9825149Abstract: The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power metal oxide semiconductor field effect transistor (MOSFET) structure and an insulated gate bipolar transistor (IGBT) structure comprising a split gate and a semi-insulating field plate. The present invention also provides manufacturing methods of the structures.Type: GrantFiled: June 21, 2016Date of Patent: November 21, 2017Inventors: Jiajin Liang, Chun Wai Ng, Johnny Kin On Sin
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Patent number: 9818845Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.Type: GrantFiled: December 13, 2016Date of Patent: November 14, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kin-On Sin, Chun-Wai Ng, Hitoshi Sumida, Yoshiaki Toyada, Akihiko Ohi, Hiroyuki Tanaka, Takeyoshi Nishimura
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Patent number: 9761545Abstract: An isolator is configured by a transmission circuit, a transformer, and a reception circuit. A first coil of the transformer is disposed on a back surface of a first semiconductor substrate; a transmission circuit and a second coil of the transformer are disposed on a front surface. The first coil is embedded within a coil trench, is led out through an embedded via-metal-film to a substrate front surface, and is electrically connected to the transmission circuit. The second coil is disposed on an insulating layer of the substrate front surface. The reception circuit is disposed on a front surface of a second semiconductor substrate. The second coil and the reception circuit are electrically connected to each other by connecting first and third electrode pads disposed respectively on the front surfaces of the first and second semiconductor substrates through wires.Type: GrantFiled: July 1, 2016Date of Patent: September 12, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Johnny Kin On Sin, Lulu Peng, Rongxiang Wu, Hitoshi Sumida, Yoshiaki Toyoda, Masashi Akahane
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Publication number: 20170250257Abstract: At edge termination region, a trench is disposed near an interface of an active region. Inside the trench, an embedded insulating film is embedded, and inside the embedded insulating film, a FP long in a direction of depth is disposed. The FP curves outwardly away from an inner side wall of the trench as a depth from a base front surface increases. At least near a bottom end of the FP, a distance between the FP and the inner side wall of the trench is greater than a width of the groove. The FP is connected to a front surface electrode that extends on the embedded insulating film. As a result, breakdown voltage may be enhanced, adverse effects of the surface charge may be reduced, and chip size may be further reduced.Type: ApplicationFiled: March 30, 2017Publication date: August 31, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Wentao YANG, Johnny Kin On SIN, Yuichi ONOZAWA
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Publication number: 20170250258Abstract: At edge termination region, a trench is disposed near an interface of an active region. Inside the trench, an embedded insulating film is embedded, and inside the embedded insulating film, a FP long in a direction of depth is disposed. The FP curves outwardly away from an inner sidewall of the trench as a depth from a base front surface increases. At least near a bottom end of the FP, a distance between the FP and the inner sidewall of trench is greater than a width of the groove. The FP is connected to a front surface electrode that extends on the embedded insulating film. As a result, breakdown voltage can be enhanced, adverse effects of the surface charge can be reduced, and chip size can be further reduced.Type: ApplicationFiled: April 25, 2017Publication date: August 31, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Wentao YANG, Johnny Kin On SIN, Yuichi ONOZAWA, Kaname MITSUZUKA
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Patent number: 9647077Abstract: A power semiconductor device comprising a first metal electrode and a second metal electrode formed on a first substrate surface of a semiconductor substrate, a semi-insulating field plate interconnecting said first and second metal electrodes, and an insulating oxide layer extending between said first and second metal electrodes and between said field plate and said semiconductor substrate, wherein said semi-insulating field plate is a titanium nitride (TiN) field plate.Type: GrantFiled: December 10, 2014Date of Patent: May 9, 2017Assignee: JSAB TECHNOLOGIES LIMITEDInventors: Johnny Kin-On Sin, Iftikhar Ahmed, Chun-Wai Ng
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Publication number: 20170092744Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.Type: ApplicationFiled: December 13, 2016Publication date: March 30, 2017Inventors: Kin-On SIN, Chun-Wai NG, Hitoshi SUMIDA, Yoshiaki TOYADA, Akihiko OHI, Hiroyuki TANAKA, Takeyoshi NISHIMURA
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Publication number: 20170040428Abstract: The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power metal oxide semiconductor field effect transistor (MOSFET) structure and an insulated gate bipolar transistor (IGBT) structure comprising a split gate and a semi-insulating field plate. The present invention also provides manufacturing methods of the structures.Type: ApplicationFiled: June 21, 2016Publication date: February 9, 2017Inventors: Jiajin LIANG, Chun Wai NG, Johnny Kin On SIN
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Patent number: 9560722Abstract: A lighting device is provided. The lighting device includes a substrate, integrated circuits (22?, 24), embedded passive components (26, 27), and a lighting component (22), the device being arranged in an architecture having three layers: an integrated circuits layer (11) including the integrated circuits (22?, 24), wherein the integrated circuits layer (11) is integrated on a first side of the substrate; an embedded passive components layer (12) including the embedded passive components (26, 27), wherein the embedded passive components (26, 27) are embedded in grooves formed in the substrate and wherein the embedded passive components are connected to the integrated circuits (22?, 24) through vias (28) in the substrate; and a bonded layer (13), including the lighting component (22), the lighting component (22) being connected to the integrated circuit layer (11) through flip-chip bonding or monolithic integration.Type: GrantFiled: March 25, 2014Date of Patent: January 31, 2017Assignee: The Hong Kong University of Science and TechnologyInventors: Chik Patrick Yue, Johnny Kin On Sin, Kei May Lau
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Patent number: 9553185Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.Type: GrantFiled: May 27, 2010Date of Patent: January 24, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kin-On Sin, Chun-Wai Ng, Hitoshi Sumida, Yoshiaki Toyada, Akihiko Ohi, Hiroyuki Tanaka, Takeyoshi Nishimura
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Publication number: 20170005046Abstract: An isolator is configured by a transmission circuit, a transformer, and a reception circuit. A first coil of the transformer is disposed on a back surface of a first semiconductor substrate; a transmission circuit and a second coil of the transformer are disposed on a front surface. The first coil is embedded within a coil trench, is led out through an embedded via-metal-film to a substrate front surface, and is electrically connected to the transmission circuit. The second coil is disposed on an insulating layer of the substrate front surface. The reception circuit is disposed on a front surface of a second semiconductor substrate. The second coil and the reception circuit are electrically connected to each other by connecting first and third electrode pads disposed respectively on the front surfaces of the first and second semiconductor substrates through wires.Type: ApplicationFiled: July 1, 2016Publication date: January 5, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Johnny Kin On SIN, Lulu PENG, Rongxiang WU, Hitoshi SUMIDA, Yoshiaki TOYODA, Masashi AKAHANE