Abstract: An integrated MOSFET-JFET device made from a Silicon-Carbide (SiC) wafer has N+ source, P body diode, and upper N regions that form vertical MOSFETs on the sidewalls of polysilicon gates. An N substrate under the upper N region forms a drift region that is pinched by the JFET to limit saturation current. Trenches are formed between MOSFETs. JFETs are formed by doping the bottom and sidewalls of the trenches to form P+ taps to the N substrate. P islands within the N substrate are formed underneath the P+ taps. These P islands are wider near the surface but are successively narrower with increased vertical spacing deeper into the N substrate. This P-island tapering provides a tapered shape to the JFET depletion region that pinches the MOSFET drift region in the N substrate to limit saturation current and yet reduce linear-region ON resistance.

Abstract: A silicon carbide diode that contains a silicon carbide substrate, a silicon carbide layer on top of the silicon carbide substrate, two first lower barrier metal portions disposed on the silicon carbide layer and separated from each other along a top surface of the silicon carbide layer, and a first higher barrier metal portion connected to the two lower barrier metal portions. The silicon carbide layer is thinner and having lower doping than the silicon carbide substrate. The first higher barrier metal portion is located between the two first lower barrier metal portions on the silicon carbide layer along a direction of the top surface of the silicon carbide layer. By reducing the leakage current at the junction barrier, the reverse breakdown voltage of the silicon carbide diode is significantly improved.

Abstract: A shielded Schottky heterojunction power transistor is made from a Silicon-Carbide (SiC) wafer with SiC epitaxial layers including a N+ source and a Silicon N-epitaxial layer under the gate with higher channel mobility than SiC. The bulk of the wafer is a N+ SiC drain contacted by backside metal. A trench is formed between heterojunction transistors. Metal contacting the N+ source is extended into the trench to form a Schottky diode with the N-SiC substrate. P+ taps on the sides of the trench connect the metal to a P-SiC body diode under the heterojunction gate, and also prevent the Schottky metal from directly contacting the P body diode. Buried P pillars with P+ pillar caps are formed under the trench Schottky diode and under the heterojunction transistors. The P pillars provide shielding by balancing charge with the N substrate, acting as dielectrics to reduce the E-field above the pillars.

Abstract: A silicon carbide diode that contains a silicon carbide substrate, a silicon carbide layer on top of the silicon carbide substrate, two first lower barrier metal portions disposed on the silicon carbide layer and separated from each other along a top surface of the silicon carbide layer, and a first higher barrier metal portion connected to the two lower barrier metal portions. The silicon carbide layer is thinner and having lower doping than the silicon carbide substrate. The first higher barrier metal portion is located between the two first lower barrier metal portions on the silicon carbide layer along a direction of the top surface of the silicon carbide layer. By reducing the leakage current at the junction barrier, the reverse breakdown voltage of the silicon carbide diode is significantly improved.

Abstract: A silicon carbide chip array containing a silicon carbide substrate; a silicon carbide layer on top of the silicon carbide substrate; a first metal contact connected to the silicon carbide substrate; and two second metal contacts connected to the first portion and the second portion respectively. The silicon carbide layer is thinner and having lower doping than the silicon carbide layer. The silicon carbide layer includes a first portion and a second portion which are separate from each other. Each one of the second metal contacts forms a semiconductor device with the first metal contact. At least one of the first and second portions contains a side face which is inclined with respect to the silicon carbide substrate. Such a configuration enhances the breakdown voltage and reduces leakage current of the resultant silicon carbide diode array.

Abstract: A silicon carbide chip array containing a silicon carbide substrate; a silicon carbide layer on top of the silicon carbide substrate; a first metal contact connected to the silicon carbide substrate; and two second metal contacts connected to the first portion and the second portion respectively. The silicon carbide layer is thinner and having lower doping than the silicon carbide layer. The silicon carbide layer includes a first portion and a second portion which are separate from each other. Each one of the second metal contacts forms a semiconductor device with the first metal contact. At least one of the first and second portions contains a side face which is inclined with respect to the silicon carbide substrate. Such a configuration enhances the breakdown voltage and reduces leakage current of the resultant silicon carbide diode array.

Abstract: The presently claimed invention provides a plating additive for electrodeposition, and the corresponding fabrication method thereof. The plating additive of the present invention enables to electroplate holes on a substrate with good height uniformity within a feature and among features at different diameters.

Abstract: A method for filling a through hole (TH) located on a substrate is provided. The TH is a continuous channel having an upper rim, a lower rim and an interior surface. In one embodiment, the method comprises steps (a)-(d). In the step (a), a conductive material (CM) is deposited over the substrate to thereby deposit a layer of the CM around the rims and on the interior surface. In the step (b), the deposited CM is etched. In particular, the etching step selectively removes more CM deposited at the rims relative to CM deposited at a mid-section of the interior surface of the channel. In the step (c), the steps (a) and (b) are optionally repeated until the channel is sealed at the mid-section by a bridge formed of CM. In the step (d), the CM is further deposited over the substrate to thereby completely fill the TH.

Abstract: The presently claimed invention provides a plating additive for electrodeposition, and the corresponding fabrication method thereof. The plating additive of the present invention enables to electroplate holes on a substrate with good height uniformity within a feature and among features at different diameters.

Abstract: The presently claimed invention provides an electrochemical analytical apparatus and a method for evaluating performance of electroplating formulations of electrolyte solutions used for via filling. The electrochemical analytical apparatus comprises an electric power generating device, an electrical output signal measurement device, an electrochemical measurement device, and a motion generator. The electrochemical measurement device of the present invention comprises a supporting structure, a cavity, a cavity electrode, and a surface electrode. The electrical output signals of the cavity electrode and the surface electrode are measured during electroplating for calculating a filling performance value. The presently claimed invention provides an accurate, fast and cost effective method for evaluating performance of electroplating formulations, following with choosing the electroplating formulation of the highest FP value for actual microvia filling process.

Abstract: This invention relates to a new compound represented by formula (I). Particularly, the new compound is used as an additive in copper electroplating. A chemical structure for the leveler, an electroplating bath containing the same, a method of preparing the additive and a method of electroplating a substrate with the electroplating bath containing the additive are disclosed. The additive compound/molecule of the present invention provides a branched structure at each ends, wherein each of the branches comprises a positively charged nitrogen moiety. The additive compound/molecule is formed by linking the branches having the positive charged nitrogen moieties to the backbone of the additive compound/molecule. This leads to a high charge density novel additive compound/molecule.

Abstract: This invention relates to a new compound represented by formula (I). Particularly, the new compound is used as an additive in copper electroplating. A chemical structure for the leveler, an electroplating bath containing the same, a method of preparing the additive and a method of electroplating a substrate with the electroplating bath containing the additive are disclosed. The additive compound/molecule of the present invention provides a branched structure at each ends, wherein each of the branches comprises a positively charged nitrogen moiety. The additive compound/molecule is formed by linking the branches having the positive charged nitrogen moieties to the backbone of the additive compound/molecule. This leads to a high charge density novel additive compound/molecule.

Abstract: The presently claimed invention provides an electrochemical analytical apparatus and a method for evaluating performance of electroplating formulations of electrolyte solutions used for via filling. The electrochemical analytical apparatus comprises an electric power generating device, an electrical output signal measurement device, an electrochemical measurement device, and a motion generator. The electrochemical measurement device of the present invention comprises a supporting structure, a cavity, a cavity electrode, and a surface electrode. The electrical output signals of the cavity electrode and the surface electrode are measured during electroplating for calculating a filling performance value. The presently claimed invention provides an accurate, fast and cost effective method for evaluating performance of electroplating formulations, following with choosing the electroplating formulation of the highest FP value for actual microvia filling process.

Abstract: This invention discloses a backside illuminated image sensor without the need to involve a mechanical grinding process or a chemical-mechanical planarization process in fabrication, and a fabricating method thereof. In one embodiment, an image sensor comprises a semiconductor substrate, a plurality of light sensing elements in the semiconductor substrate, and a cavity formed in the semiconductor substrate. The light sensing elements are arranged in a substantially planar manner. The cavity has a base surface overlying the light sensing elements. The presence of the cavity allows the image to reach the light sensing elements through the cavity base surface. The cavity can be fabricated by etching the semiconductor substrate. Agitation may also be used when carrying out the etching.

Abstract: This invention discloses a backside illuminated image sensor without the need to involve a mechanical grinding process or a chemical-mechanical planarization process in fabrication, and a fabricating method thereof. In one embodiment, an image sensor comprises a semiconductor substrate, a plurality of light sensing elements in the semiconductor substrate, and a cavity formed in the semiconductor substrate. The light sensing elements are arranged in a substantially planar manner. The cavity has a base surface overlying the light sensing elements. The presence of the cavity allows the image to reach the light sensing elements through the cavity base surface. The cavity can be fabricated by etching the semiconductor substrate. Agitation may also be used when carrying out the etching.

Abstract: An enterprise medical billing system receives patient identifying and charge information from a variety of sources, associates the charge data with a guarantor, provides a consolidated statement to the guarantor, and allocates portions of a received payment to the variety of sources based on a series of configurable payment rules.