Abstract: Embodiments herein describe techniques for assigning address ranges to ports in switches forming a packet protocol switch network in an integrated circuit. Instead of relying on a designer to provide the addresses, the integrated circuit can include an address bus which is incremented as addresses are assigned to the ports. In one embodiment, the port addresses are assigned from a root device and defines the address range of each branch port and the address of each endpoint in the network. As the address bus reaches an endpoint, an adder in the endpoint increments the value of the address bus (e.g., the current address). The address bus may use serial or parallel data communication to assign the addresses. In another embodiment, instead of using a separate address bus, a data bus typically used for packet communication assigns the addresses to the ports in the network.

Abstract: A multi-chip structure that implements a configurable Network-on-Chip (NoC) for communication between chips is described herein. In an example, an apparatus includes a first chip comprising a first processing system and a first configurable NoC connected to the first processing system, and includes a second chip comprising a second processing system and a second configurable NoC connected to the second processing system. The first and second configurable NoCs are connected together via an external connector. The first and second processing systems are operable to obtain first and second information from off of the first and second chip and configure the first and second configurable NoCs based on the first and second information, respectively. The first and second processing systems are communicatively coupled with each other via the first and second configurable NoCs when the first and second configurable NoCs are configured based on the first and second information, respectively.

Abstract: A multi-chip structure that implements a configurable Network-on-Chip (NoC) for communication between chips is described herein. In an example, an apparatus includes a first chip comprising a first processing system and a first configurable NoC connected to the first processing system, and includes a second chip comprising a second processing system and a second configurable NoC connected to the second processing system. The first and second configurable NoCs are connected together via an external connector. The first and second processing systems are operable to obtain first and second information from off of the first and second chip and configure the first and second configurable NoCs based on the first and second information, respectively. The first and second processing systems are communicatively coupled with each other via the first and second configurable NoCs when the first and second configurable NoCs are configured based on the first and second information, respectively.

Abstract: Some embodiments provide dynamic circuits with dynamic nodes that may float during a disable mode to reduce leakage.

Abstract: Some embodiments provide dynamic circuits with dynamic nodes that may float during a disable mode to reduce leakage.

Abstract: According to some embodiments, a parity check is provided for ternary content addressable memory. For example, it may be arranged for a read request to be transmitted to a ternary content addressable memory unit. Data content may then be received from the memory unit in response to the read request, a parity check may be performed on the data content. According to some embodiments, parity information may be masked when the memory unit is queried.

Abstract: According to some embodiments, a parity check is provided for ternary content addressable memory.