Abstract: A fast algorithm is used to study the transient behavior due to a step-like pulse applied to a nano-chip. This algorithm is carried out on a computer and consists of two parts: The algorithm I reduces the computational complexity to T0N3 for large systems as long as T<N; The algorithm II employs the fast multipole technique and achieves scaling T0N3 whenever T<N2 beyond which it becomes T log2 N for even longer time. Hence it is of order O(1) if T<N2. Benchmark calculation has been done on graphene nanoribbons with N=104 and T=108. This new algorithm allows many large scale transient problems to be solved, including magnetic tunneling junctions and ferroelectric tunneling junctions that could not be achieved before, and using less computing capacity.

Abstract: A fast algorithm is used to study the transient behavior due to the step-like pulse. This algorithm consists of two parts: The algorithm I reduces the computational complexity to T0N3 for large systems as long as T<N; The algorithm II employs the fast multipole technique and achieves scaling T0N3whenever T<N2 beyond which it becomes T log2 N for even longer time. Hence it is of order O(1) if T<N2. Benchmark calculation has been done on graphene nanoribbons with N=104 and T=108. This new algorithm allows many large scale transient problems to be solved, including magnetic tunneling junctions and ferroelectric tunneling junctions that could not be achieved before.

Abstract: In a method of refurbishing a deposition target, a surface of the target is provided in a process zone. An electrical arc is generated in the process zone, and a consumable metal wire is inserted into the process zone to form liquefied metal. A pressurized gas is injected into the process zone to direct the liquefied metal toward the surface of the target to splatter the liquefied metal on the surface, thereby forming a coating having the metal on at least a portion of the surface of the target that exhibits reduced contamination from the environment.

Abstract: A coated aluminum component for a substrate processing chamber comprises an aluminum component having a surface; a first aluminum oxide layer formed on the surface of the aluminum component, the aluminum oxide layer having a surface comprising penetrating surface features; and a second aluminum oxide layer on the first aluminum oxide layer, the second aluminum oxide layer substantially completely filling the penetrating surface features of the first aluminum oxide layer. A method of forming the coated aluminum component is also described.

Abstract: The specification describes an integrated passive device (IPD) that is formed on a polysilicon substrate. A method for making the IPD is disclosed wherein the polysilicon substrate is produced starting with a single crystal handle wafer, depositing a thick substrate layer of polysilicon on one or both sides of the starting wafer, forming the IPD on one of the polysilicon substrate layers, and removing the handle wafer. In a preferred embodiment the single crystal silicon handle wafer is a silicon wafer rejected from a single crystal silicon wafer production line.

Abstract: The specification describes an integrated passive device (IPD) designed to allow implementation of cellular RF and Wi-Fi RF in a single hand held device. To address the problem of RF interference a thin film RF high rejection bandpass filter is formed in an IPD implementation. The IPD implementation preferably uses silicon as the substrate material. This allows the thin film RF high rejection bandpass filter to be made using silicon processing technology, and thus produce low cost filters that still meet stringent performance requirements demanded due to the co-existing RF units. In preferred embodiments of the invention, wafer level processing using silicon substrates adds to the cost effective manufacture of the highly functional IPDs.

Abstract: The specification describes a silicon-on-silicon interconnection arrangement to implement high performance RF impedance matching using off-chip passive components. The RF sections of the system are dis-integrated into separate RF functional chips, and the functional chips are flip-chip mounted on a high resistivity silicon intermediate interconnect substrate (SIIS). The passive devices for the impedance matching networks are built into the high resistivity SIIS using thin-film technology.

Abstract: A polishing pad conditioner comprises a base and a pad conditioning face on the base. The conditioning face comprises central and peripheral regions. Abrasive spokes having a substantially constant width of abrasive particles, extend from the central to the peripheral region. The spokes are symmetric and radially spaced apart from one another, and may have a variety of shapes. The conditioning face can also have a cutout inlet channel to receive polishing slurry when the conditioning face is rubbed against a polishing pad, a conduit to receive the polishing slurry from the cutout inlet channel, and an outlet on the peripheral edge of the base to discharge the received polishing slurry.

Abstract: The present invention provides a method and apparatus for precleaning a patterned substrate with a plasma comprising a mixture of argon, helium, and hydrogen. Addition of helium to the gas mixture of argon and hydrogen surprisingly increases the etch rate in comparison to argon/hydrogen mixtures. Etch rates are improved for argon concentrations below about 75% by volume. RF power is capacitively and inductively coupled to the plasma to enhance control of the etch properties. Argon, helium, and hydrogen can be provided as separate gases or as mixtures.

Abstract: In a magnetron sputtering chamber, a substrate is placed in the chamber and a deposition shield is maintained about the substrate to shield internal surfaces in the chamber. The deposition shield has a textured surface that may be formed by a hot pressing process or by a coating process, and that allows the accumulated sputtered residues to stick thereto without flaking off. An electrical power is applied to a high density sputtering target facing the substrate to form a plasma in the chamber while a rotating magnetic field of at least about 300 Gauss is applied about the target to sputter the target. Advantageously, the sputtering process cycle can be repeated for at least about 8,000 substrates without cleaning the internal surfaces in the chamber, and even while still generating an average particle count on each processed substrate of less than 1 particle per 10 cm2 of substrate surface area.

Abstract: The present invention generally provides a method for improving fill and electrical performance of metals deposited on patterned dielectric layers. Apertures such as vias and trenches in the patterned dielectric layer are etched to enhance filling and then cleaned in the same chamber to reduce metal oxides within the aperture.

Abstract: Embodiments of the present invention provide a method, article of manufacture, and apparatus for processing semiconductor wafers. The method includes preheating a semiconductor wafer in two types of chambers. In one embodiment, a first preheating chamber is a load lock and a second preheating chamber is a transition chamber. Semiconductor wafer processing systems which can perform embodiments of the method are presented.

Abstract: A method of refurbishing a deposition target having a surface with an eroded region involves measuring a depth profile of the eroded region. A target material is then provided to the eroded region in relation to the measured depth profile to refurbish the target by filling the eroded region with the target material. The process provides improved refurbishment of eroded target surfaces with higher refurbishing precision and less waste of valuable target material.

Abstract: The specification describes an integrated passive device (IPD) that is formed on a polysilicon substrate. A method for making the IPD is disclosed wherein the polysilicon substrate is produced starting with a single crystal handle wafer, depositing a thick substrate layer of polysilicon on one or both sides of the starting wafer, forming the IPD on one of the polysilicon substrate layers, and removing the handle wafer. In a preferred embodiment the single crystal silicon handle wafer is a silicon wafer rejected from a single crystal silicon wafer production line.

Abstract: A recycled polishing pad conditioner comprises a base plate and a reversed abrasive disc that is flipped over from its original configuration. The reversed disc comprises an exposed abrasive face having an unused abrasive face comprising abrasive particles. A bond face of the disc is affixed to the base plate, the bond face comprising a used abrasive face that was previously used to condition polishing pads. Also described is a pad conditioner having an abrasive face comprising exposed portions of abrasive particles, with at least about 60% of the abrasive particles having a crystalline structure with substantially the same crystal symmetry.

Abstract: Increased sidewall coverage by a sputtered material is achieved by generating an ionizing plasma in a relatively low pressure sputtering gas. By reducing the pressure of the sputtering gas, it is believed that the ionization rate of the deposition material passing through the plasma is correspondingly reduced which in turn is believed to increase the sidewall coverage by the underlayer. Although the ionization rate is decreased, sufficient bottom coverage of the by the material is maintained. In an alternative embodiment, increased sidewall coverage by the material may be achieved even in a high density plasma chamber by generating the high density plasma only during an initial portion of the material deposition. Once good bottom coverage has been achieved, the RF power to the coil generating the high density plasma may be turned off entirely and the remainder of the deposition conducted without the high density plasma.

Abstract: The specification describes a flexible membrane test apparatus and test method for high-speed IC chips. The method and apparatus rely on locating the reference components of the test circuit very close to the contact pads of the IC chip under test. This is achieved in one embodiment by locating those components adjacent to the flexible membrane. In another embodiment, the reference components may be attached to the membrane itself, so the length of the runners connecting the contact points of the tester and the critical reference components is optimally reduced. In yet a further embodiment, the entire test circuit, in the form of an IC test chip, is located on the membrane.

Abstract: A positive pressure gradient is maintained across an open access port of an interface chamber such as a load lock chamber which provides an interface between a low pressure chamber such as a transfer or buffer chamber, and a high pressure area such as a staging area or factory interface area. When the access port of the interface chamber is open to the high-pressure area, the positive pressure gradient may be used in some applications to inhibit the flow of gasses from the high-pressure area into the interior of the interface chamber.

Abstract: A method of controlling intrinsic stress in metal films deposited on a substrate using physical vapor deposition (PVD) techniques is disclosed. The film stress is controlled, by applying a bias power to the substrate during the deposition process. The magnitude of the bias power applied to the substrate modulates the film stress such that as-deposited material layers have an intrinsic stress that may be either tensile or compressive. Also, a reflected bias power may be applied to the substrate during the deposition process, in addition to the bias power. The magnitude of the reflected bias power in combination with the bias power also modulates the film stress such that as-deposited material layers have an intrinsic stress that may be either tensile or compressive.

Abstract: A positive pressure gradient is maintained across an open access port of an interface chamber such as a load lock chamber which provides an interface between a low pressure chamber such as a transfer or buffer chamber, and a high pressure area such as a staging area or factory interface area. When the access port of the interface chamber is open to the high-pressure area, the positive pressure gradient may be used in some applications to inhibit the flow of gasses from the high-pressure area into the interior of the interface chamber.