Abstract: Systems, devices, and methods, including logic and/or executable instructions are described in connection with a buffer circuit. One buffer circuit includes a flip-flop based first-in first-out (FIFO) buffer having an input and an output, selection logic coupled in series with the FIFO buffer input, and a random access memory (RAM) FIFO coupled in parallel with the selection logic. The selection logic diverts incoming data to the RAM FIFO after the FIFO buffer is filled to a first capacity level, and reloads the FIFO buffer using data from the RAM FIFO until the RAM FIFO is emptied to a second capacity level. Data is extracted without read data latency from the output of the FIFO buffer as an output of the buffer circuit.

Abstract: Systems, devices, and methods, including logic and/or executable instructions are described in connection with a buffer circuit. One buffer circuit includes a flip-flop based first-in first-out (FIFO) buffer having an input and an output, selection logic coupled in series with the FIFO buffer input, and a random access memory (RAM) FIFO coupled in parallel with the selection logic. The selection logic diverts incoming data to the RAM FIFO after the FIFO buffer is filled to a first capacity level, and reloads the FIFO buffer using data from the RAM FIFO until the RAM FIFO is emptied to a second capacity level. Data is extracted without read data latency from the output of the FIFO buffer as an output of the buffer circuit.