Abstract: This disclosure provides systems, methods, and devices for image signal processing that support synchronizing configurations between an image sensor and an image signal processor (ISP). In a first aspect, a method of image processing includes, for each stage of an ISP pipeline, configuring processing in the stage based on metadata in the image data from the image sensor. For example, a capture configuration identifier associated with an image frame may be used to reconfigure the ISP stage, such that the ISP stage configuration is updated in synchronization with image data received from an image sensor that has changed configurations. Other aspects and features are also claimed and described.

Abstract: Techniques are described for interrupt handling. A device can obtain, at a first context buffer associated with a first interrupt handler, first processing configuration data associated with a first sensor; obtain, at a second context buffer associated with a second interrupt handler, second processing configuration data associated with a second sensor; obtain, at the first interrupt handler, an error indication associated with the first sensor; perform, by the first interrupt handler, based on the error indication, an error handling operation (where the error handling operation comprises flushing the first context buffer and/or invalidating the first processing configuration data in the first context buffer); obtain, at the second interrupt handler, during a time window interval between obtaining the error indication and a completion time of the error handling operation, from the second sensor, an interrupt request (IRQ); and output, based on the IRQ, the second processing configuration data to a processor.

Abstract: This disclosure provides systems, methods, and devices for image signal processing that support synchronizing configurations between an image sensor and an image signal processor (ISP). In a first aspect, a method of image processing includes, for each stage of an ISP pipeline, configuring processing in the stage based on metadata in the image data from the image sensor. For example, a capture configuration identifier associated with an image frame may be used to reconfigure the ISP stage, such that the ISP stage configuration is updated in synchronization with image data received from an image sensor that has changed configurations. Other aspects and features are also claimed and described.

Abstract: Techniques are described for interrupt handling. A device can obtain, at a first context buffer associated with a first interrupt handler, first processing configuration data associated with a first sensor; obtain, at a second context buffer associated with a second interrupt handler, second processing configuration data associated with a second sensor; obtain, at the first interrupt handler, an error indication associated with the first sensor; perform, by the first interrupt handler, based on the error indication, an error handling operation (where the error handling operation comprises flushing the first context buffer and/or invalidating the first processing configuration data in the first context buffer); obtain, at the second interrupt handler, during a time window interval between obtaining the error indication and a completion time of the error handling operation, from the second sensor, an interrupt request (IRQ); and output, based on the IRQ, the second processing configuration data to a processor.

Abstract: A predicate register is assigned as an exception handling predicate register. An exception may be detected when executing the machine readable instructions. An exception state for the exception is stored in the exception handling predicate register.

Abstract: A method includes generating an N-bit generated hash key for an M-bit search key. A data value associated with a matching hash key stored in a content addressable memory is retrieved. The matching hash key is then validated. The content addressable memory supports 2k entries, wherein M>N>k.

Abstract: One embodiment disclosed relates to an integrated circuit including on-chip logic analyzer circuitry. The on-chip logic analyzer circuitry includes a triggering circuit configured to receive a source data signal and start/stop timing signals. The on-chip logic analyzer circuitry further includes a compression circuit configured to receive an uncompressed data signal from the triggering circuit and to perform compression so as to form a compressed data signal. Other embodiments, aspects and features are also disclosed.

Abstract: Timing of a write and read strobes for a memory having a double data rate (DDR) interface are automatically adjusted using write-read operations. A first and a second value of the write and read strobes are determined for a first write-read operation having the read data match the write data. A second write-read operation is performed for each of a plurality of third values for the write strobe at the second value for the read strobe set. A center of the third values having the read data match the write data is determined. A third write-read operation is performed for each of a plurality of fifth values for the read strobe at the fourth value of the write strobe. A center of the fifth values having the read data match the write data is determined. The timing of the write and read strobes are set to the centers.

Abstract: A method includes generating an N-bit generated hash key for an M-bit search key. A data value associated with a matching hash key stored in a content addressable memory is retrieved. The matching hash key is then validated. The content addressable memory supports 2k entries, wherein M>N>k.

Abstract: One embodiment disclosed relates to an integrated circuit including on-chip logic analyzer circuitry. The on-chip logic analyzer circuitry includes a triggering circuit configured to receive a source data signal and start/stop timing signals. The on-chip logic analyzer circuitry further includes a compression circuit configured to receive an uncompressed data signal from the triggering circuit and to perform compression so as to form a compressed data signal. Other embodiments, aspects and features are also disclosed.

Abstract: Timing of a write and read strobes for a memory having a double data rate (DDR) interface are automatically adjusted using write-read operations. A first and a second value of the write and read strobes are determined for a first write-read operation having the read data match the write data. A second write-read operation is performed for each of a plurality of third values for the write strobe at the second value for the read strobe set. A center of the third values having the read data match the write data is determined. A third write-read operation is performed for each of a plurality of fifth values for the read strobe at the fourth value of the write strobe. A center of the fifth values having the read data match the write data is determined. The timing of the write and read strobes are set to the centers.