Abstract: A semiconductor device includes first and second nitride semiconductor layers, a source, a drain, a gate structure, first and second p-type doped nitride semiconductor compound islands. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The source, the drain, and the gate structure are disposed on the second nitride semiconductor layer. The drain viewed in a direction normal to the second nitride semiconductor layer extends longitudinally in an extending direction. The gate structure is between the source and the drain. The first p-type doped nitride semiconductor compound islands are disposed on the second nitride semiconductor layer and arranged adjacent to the drain along the extending direction. The second p-type doped nitride semiconductor compound island is disposed between the gate structure and the second nitride semiconductor layer.

Abstract: Some embodiments of the disclosure provide a semiconductor device. The semiconductor device comprises: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer and having a band gap greater than a band gap of the first nitride semiconductor layer; a group III-V dielectric layer disposed on the second nitride semiconductor layer; a gate electrode disposed on the second nitride semiconductor layer; and a first passivation layer disposed on the group III-V dielectric layer, wherein the group III-V dielectric layer is separated from the gate electrode by the first passivation layer.

Abstract: A semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer, the second nitride semiconductor layer forming a first recess and a second recess; and an electrode disposed on the second nitride semiconductor layer and comprising an element; wherein the electrode is disposed in the first recess and the second recess.

Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional hole gas (2DHG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DHG.

Abstract: An automated concrete cube processing system. The system comprises a curing stage including a water tank arranged to facilitate curing of a plurality of concrete cubes for a predetermined period of time; a drying stage arranged to facilitate drying of the plurality of concrete cubes upon completion of curing process; a measurement stage arranged to facilitate measuring of dimensions and a weight of each of the plurality of concrete cubes; a compression stage arranged to facilitate undertaking of a compressive strength test on each of the plurality of concrete cubes; and a transportation module arranged to transfer the plurality of concrete cubes among different stages.

Abstract: Some embodiments of the present disclosure provide a semiconductor device including a channel layer, a barrier layer, a p-type doped III-V layer, a gate, a drain, and a doped semiconductor layer. The barrier layer is disposed on the channel layer. The p-type doped III-V layer is disposed on the barrier layer. The gate is disposed on the p-type doped III-V layer. The drain is disposed on the barrier layer. The doped semiconductor layer is disposed on the barrier layer and is covered by the drain. The drain has a first portion located between the p-type doped III-V layer and an entirety of the doped semiconductor layer.

Abstract: A nitride-based semiconductor device includes a first and a second nitride-based semiconductor layers, a source electrode, a gate electrode, and a drain structure. The drain structure includes a first doped nitride-based semiconductor layer, an ohmic contact electrode, and a conductive layer. The first doped nitride-based semiconductor layer is in contact with the second nitride-based semiconductor layer to form a first contact interface. The ohmic contact electrode is in contact with the second nitride-based semiconductor layer to form a second contact interface. The conductive layer includes metal and in contact with the second nitride-based semiconductor layer to form a metal-semiconductor junction therebetween. The conductive layer is connected to the first doped nitride-based semiconductor layer and the ohmic contact electrode, and the ohmic contact interface is farther away from the gate electrode than the first contact interface and the second contact interface.

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure, a first spacer, a second spacer and a drain electrode. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The first spacer is disposed adjacent to a first surface of the gate structure. The second spacer is disposed adjacent to a second surface of the gate structure. The drain electrode is disposed relatively adjacent to the second spacer than the first space. The first spacer has a first length, and the second spacer has a second length greater than the first length along the first direction.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-V material layer and a gate structure. The gate structure includes a first portion and a second portion on the first portion. The first portion is on the III-V material layer. The first portion has a first surface and a second surface opposite to the first surface and adjacent to the III-V material layer. A length of the second surface of the first portion of the gate structure is less than a length of the first surface of the first portion of the gate structure. A length of the second portion of the gate structure is less than the length of the first portion of the gate structure.

Abstract: The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a passivation layer covering the first gate conductor, and a second gate conductor disposed on the passivation layer and on a second region of the second nitride semiconductor layer, wherein the first region is laterally spaced apart from the second region.

Abstract: A III-nitride-based semiconductor packaged structure includes a lead frame, an adhesive layer, a III-nitride-based die, an encapsulant, and at least one bonding wire. The lead frame includes a die paddle and a lead. The die paddle has first and second recesses arranged in a top surface of the die paddle. The first recesses are located adjacent to a relatively central region of the top surface. The second recesses are located adjacent to a relatively peripheral region of the top surface. The first recess has a shape different from the second recess from a top-view perspective. The adhesive layer is disposed on the die paddle to fill into the first recesses. The III-nitride-based die is disposed on the adhesive layer. The encapsulant encapsulates the lead frame and the III-nitride-based die. The second recesses are filled with the encapsulant. The bonding wire is encapsulated by the encapsulant.

Abstract: The present invention relates to a semiconductor device having an improved gate leakage current. The semiconductor device includes: a substrate; a first nitride semiconductor layer, positioned above the substrate; a second nitride semiconductor layer, positioned above the first nitride semiconductor layer and having an energy band gap greater than that of the first nitride semiconductor layer; a source contact and a drain contact, positioned above the second nitride semiconductor layer; a doped third nitride semiconductor layer, positioned above the second nitride semiconductor layer and between the drain contact and the source contact; and a gate electrode, positioned above the doped third nitride semiconductor layer, where the doped third nitride semiconductor layer has at least one protrusion extending along a direction substantially parallel to an interface between the first nitride semiconductor layer and the second nitride semiconductor layer, thereby improving the gate leakage current phenomenon.

Abstract: A nitride semiconductor device includes a semiconductor carrier, a first nitride-based chip, and first conformal connecting structures. The first nitride-based chip is disposed over the semiconductor carrier. The semiconductor carrier has a first planar surface. The first nitride-based chip has a second planar surface, first conductive pads, and first slanted surfaces. The first conductive pads are disposed in the second planar surface. The first slanted surfaces connect the second planar surface to the first planar surface. The first conformal connecting structures are disposed on the first planar surface and the first nitride-based chip. First obtuse angles are formed between the second planar surface and the first slanted surfaces. Each of the first conformal connecting structures covers one of the first slanted surfaces of the first nitride-based chip and one of the first obtuse angles and is electrically connected to the first conductive pads.

Abstract: A nitride-based semiconductor device includes a buffer, a first nitride-based semiconductor layer, a shield layer, a second nitride-based semiconductor layer, a pair of S/D electrodes, and a gate electrode. The first nitride-based semiconductor layer is disposed over the buffer and forms a first interface with the buffer. The shield layer includes a first isolation compound and is interposed between the buffer and the first nitride-based semiconductor layer. The first isolation compound has a bandgap greater than a bandgap of the buffer and greater than a bandgap of the first nitride-based semiconductor layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap less than the bandgap of the first isolation compound and greater than the bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.

Abstract: A semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer, the second nitride semiconductor layer forming a first recess and a second recess; and an electrode disposed on the second nitride semiconductor layer and comprising an element; wherein the electrode is disposed in the first recess and the second recess.

Abstract: Some embodiments of the disclosure provide a semiconductor device. The semiconductor device comprises: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer and having a band gap greater than a band gap of the first nitride semiconductor layer; a group III-V dielectric layer disposed on the second nitride semiconductor layer; a gate electrode disposed on the second nitride semiconductor layer; and a first passivation layer disposed on the group III-V dielectric layer, wherein the group III-V dielectric layer is separated from the gate electrode by the first passivation layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional hole gas (2DHG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DHG.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, a gate electrode, and a third nitride-based semiconductor layer. The first nitride-based semiconductor layer has at least one trench. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and spaced apart from the trench. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The gate electrode is disposed above the second nitride-based semiconductor layer and between the source and drain electrodes, so as to at least define a drift region between the gate electrode and the drain electrode and overlaps with the trench. The third nitride-based semiconductor layer is at least disposed in the trench and extends upward from the trench to make contact with the second nitride-based semiconductor layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DEG.

Abstract: A semiconductor device includes a first and a second nitride-based semiconductor layers and a gate structure. The gate structure includes an outer spacer, an inner spacer and a gate electrode. The outer spacer has at least two opposite inner sidewalls to define a gate trench. The inner spacer is within the gate trench. The gate electrode disposed in the gate trench and covered by the inner spacer, wherein the inner spacer and the gate electrode extend downward to collaboratively form a bottom portion of the gate structure with a first width greater than a second width of a bottom surface of the gate electrode.