Patents by Inventor Kingo Suzuki

Kingo Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7663151
    Abstract: A light emitting device chip is obtained by dicing a light emitting device wafer having a light emitting layer section 24 based on a double heterostructure in which a first-conductivity-type cladding layer 6, an active layer 5 and an second-conductivity-type cladding layer 4, each of which being composed of a compound semiconductor having a composition allowing lattice matching with GaAs, out of compound semiconductors expressed by formula (AlxGa1-x)yIn1-yP (where, 0?x?1, 0?y?1), are stacked in this order, and having the (100) surface appeared on the main surface thereof, and GaP transparent semiconductor layers 20, 90 stacked on the light emitting layer section 24 as being agreed with the crystal orientation thereof, so that the {100} surfaces appear on the side faces of the GaP transparent semiconductor layer.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: February 16, 2010
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Ikeda, Kingo Suzuki, Akio Nakamura
  • Patent number: 7579205
    Abstract: A light emitting device wafer having a light emitting layer section 24 having an AlGaInP-base double heterostructure, and a GaP light extraction layer 20 disposed on the light emitting layer section so as to allow a first main surface thereof to compose a first main surface of the wafer is fabricated so that the first main surface of the GaP light extraction layer appears as the (100) surface. The first main surface of the GaP light extraction layer 20 composed of the (100) surface is etched using an etching solution for surface roughening to thereby form surface roughening projections 40f. Accordingly, there can be provided a method of fabricating a light emitting device having the GaP light extraction layer agreed with the (100) main surface, capable of readily subjecting the (100) main surface to surface roughening.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: August 25, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Ikeda, Kingo Suzuki, Akio Nakamura
  • Publication number: 20080061307
    Abstract: A light emitting device wafer having a light emitting layer section 24 having an AlGaInP-base double heterostructure, and a GaP light extraction layer 20 disposed on the light emitting layer section so as to allow a first main surface thereof to compose a first main surface of the wafer is fabricated so that the first main surface of the GaP light extraction layer appears as the (100) surface. The first main surface of the GaP light extraction layer 20 composed of the (100) surface is etched using an etching solution for surface roughening to thereby form surface roughening projections 40f. Accordingly, there can be provided a method of fabricating a light emitting device having the GaP light extraction layer agreed with the (100) main surface, capable of readily subjecting the (100) main surface to surface roughening.
    Type: Application
    Filed: April 13, 2005
    Publication date: March 13, 2008
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Ikeda, Kingo Suzuki, Akio Nakamura
  • Publication number: 20070224714
    Abstract: A light emitting device chip is obtained by dicing a light emitting device wafer having a light emitting layer section 24 based on a double heterostructure in which a first-conductivity-type cladding layer 6, an active layer 5 and an second-conductivity-type cladding layer 4, each of which being composed of a compound semiconductor having a composition allowing lattice matching with GaAs, out of compound semiconductors expressed by formula (AlxGa1-x)yIn1-yP (where, 0?x?1, 0?y?1), are stacked in this order, and having the (100) surface appeared on the main surface thereof, and GaP transparent semiconductor layers 20, 90 stacked on the light emitting layer section 24 as being agreed with the crystal orientation thereof, so that the {100} surfaces appear on the side faces of the GaP transparent semiconductor layer.
    Type: Application
    Filed: April 13, 2005
    Publication date: September 27, 2007
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Ikeda, Kingo Suzuki, Akio Nakamura
  • Patent number: 6995401
    Abstract: A light emitting device having an oxide transparent electrode layer as an emission drive electrode, and designed so that damage possibly occurs during bonding of electrode wires to the bonding pads is less influential to a light emitting layer portion is disclosed. The light emitting device has the light emitting layer portion composed of a compound semiconductor and has a double heterostructure in which a first-conductivity-type cladding layer, an active layer and a second-conductivity-type cladding layer are stacked in this order; and the light emitting layer portion is applied with emission drive voltage through an oxide transparent electrode layer formed so as to cover the main surface of the second-conductivity-type cladding layer. A bonding pad composed of a metal is disposed on the oxide transparent electrode layer, and to the bonding pad an electrode wire for current supply is bonded.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: February 7, 2006
    Assignees: Shin-Etsu Handotai Co., Ltd., Nanoteco Corporation
    Inventors: Masato Yamada, Nobuhiko Noto, Masanobu Takahashi, Kingo Suzuki, Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
  • Publication number: 20040206961
    Abstract: A light emitting device having an oxide transparent electrode layer as an emission drive electrode, and designed so that damage possibly occurs during bonding of electrode wires to the bonding pads is less influential to a light emitting layer portion is disclosed. The light emitting device has the light emitting layer portion composed of a compound semiconductor and has a double heterostructure in which a first-conductivity-type cladding layer, an active layer and a second-conductivity-type cladding layer are stacked in this order; and the light emitting layer portion is applied with emission drive voltage through an oxide transparent electrode layer formed so as to cover the main surface of the second-conductivity-type cladding layer. A bonding pad composed of a metal is disposed on the oxide transparent electrode layer, and to the bonding pad an electrode wire for current supply is bonded.
    Type: Application
    Filed: October 22, 2003
    Publication date: October 21, 2004
    Applicants: Shin-Etsu Handotai Co., Ltd., Nanoteco Corporation
    Inventors: Masato Yamada, Nobuhiko Noto, Masanobu Takahashi, Kingo Suzuki, Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
  • Patent number: 6700139
    Abstract: The main surface on the side of a p-type layer of a GaP-base semiconductor is defined as a first main surface, and the main surface opposite thereto as a second main surface. The second main surface is lapped and then etched using aqua regia to thereby collectively form thereon specular concave curved surfaces which swell inwardly into the semiconductor substrate in order to enhance total reflection of light. On the other hand, the area on the surface of semiconductor substrate excluding that for forming a first contact layer and excluding the second main surface are subjected to anisotropic etching to thereby collectively form outwardly-swelling convex curved surfaces in order to reduce total reflection of light. A second contact layer (second electrode) to be formed on the second main surface is composed of an alloy of Au, Si and Ni, and a first contact layer to be formed on the first main surface is composed of an alloy of Au as combined with either of Be and Zn.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: March 2, 2004
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kingo Suzuki, Hitoshi Ikeda, Yasutsugu Kaneko
  • Publication number: 20030047745
    Abstract: The main surface on the side of a p-type layer of a GaP-base semiconductor is defined as a first main surface, and the main surface opposite thereto as a second main surface. The second main surface is lapped and then etched using aqua regia to thereby collectively form thereon specular concave curved surfaces which swell inwardly into the semiconductor substrate in order to enhance total reflection of light. On the other hand, the area on the surface of semiconductor substrate excluding that for forming a first contact layer and excluding the second main surface are subjected to anisotropic etching to thereby collectively form outwardly-swelling convex curved surfaces in order to reduce total reflection of light. A second contact layer (second electrode) to be formed on the second main surface is composed of an alloy of Au, Si and Ni, and a first contact layer to be formed on the first main surface is composed of an alloy of Au as combined with either of Be and Zn.
    Type: Application
    Filed: August 27, 2002
    Publication date: March 13, 2003
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kingo Suzuki, Hitoshi Ikeda, Yasutsugu Kaneko